source: rtems/bsps/m68k/gen68340/include/m68340.inc @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*----------------------------------------------------------------------------
2* file name: M68340.INC                                 JC RAHUEL CNET/DSM/TAM/CAT
3*
4* MC68340 BCC  Board Support Package
5*
6* date: 1/12/1993                                       
7*
8* Copyright 1989, Ready Systems FRANCE
9*
10* Supports: VRTX32 and RTscope
11*
12* Related Board: MOTOROLA BCC M68340
13*
14* Description:  EQUATES FOR 68340 DEVICES
15*
16* Changes:
17*       - Geoffroy Montel (g_montel@yahoo.com) :
18*         changed EQU syntax for GNU as
19*
20*----------------------------------------------------------------------------*/
21
22/************************************************
23 * ATTENTION: must match defs. in C header file *
24 ************************************************/
25
26/* -- SIM equates --    system integration module */
27.equ BASE_REG, 0x3FF00 
28.equ BASE_SIM, 0xEFFFF000
29.equ SIM_MCR, 0x000     /* module configuration register */     
30.equ SIM_SYNCR, 0x004   /* clock synthesizer control register */       
31.equ SIM_AVR, 0x006     /* autovector register */       
32.equ SIM_RSR, 0x007     /* reset status register */     
33
34/* -- Port A -- */
35.equ SIM_PORTA, 0x011   /* port A data */       
36.equ SIM_DDRA, 0x013    /* port A direction data */     
37.equ SIM_PPRA1, 0x015   /* Port A pin assignement 1 */ 
38.equ SIM_PPRA2, 0x017   /* Port A pin assignement 2 */ 
39
40/* -- Port B -- */
41.equ SIM_PORTB, 0x019   /* port B data */       
42.equ SIM_PORTB1, 0x01B  /* port B data auxiliary */     
43.equ SIM_DDRB, 0x01D    /* port B direction data */     
44.equ SIM_PPRB, 0x01F    /* Port B pin assignement */
45.equ SIM_SWIV, 0x020    /* SW interrupt vector */       
46.equ SIM_SYPCR, 0x021   /* System protection control register */       
47.equ SIM_PICR, 0x022    /* Periodic interrupt control register */       
48.equ SIM_PITR, 0x024    /* Periodic interrupt timing register */       
49.equ SIM_SWSR, 0x027    /* Sofware service */   
50
51/* -- Chip select -- */
52.equ SIM_MASKH0, 0x040  /* mask register CS0 */
53.equ SIM_MASKL0, 0x042  /* mask register CS0 */
54.equ SIM_ADDRH0, 0x044  /* base address CS0 */ 
55.equ SIM_ADDRL0, 0x046  /* base address CS0 */ 
56.equ SIM_MASKH1, 0x048  /* mask register CS1 */
57.equ SIM_MASKL1, 0x04A  /* mask register CS1 */
58.equ SIM_ADDRH1, 0x04C  /* base address CS1 */ 
59.equ SIM_ADDRL1, 0x04E  /* base address CS1 */ 
60.equ SIM_MASKH2, 0x050  /* mask register CS2 */
61.equ SIM_MASKL2, 0x052  /* mask register CS2 */
62.equ SIM_ADDRH2, 0x054  /* base address CS2 */ 
63.equ SIM_ADDRL2, 0x056  /* base address CS2 */ 
64.equ SIM_MASKH3, 0x058  /* mask register CS3 */
65.equ SIM_MASKL3, 0x05A  /* mask register CS3 */
66.equ SIM_ADDRH3, 0x05C  /* base address CS3 */ 
67.equ SIM_ADDRL3, 0x05E  /* base address CS3 */ 
68
69/* -- TIMERS  equates -- */
70
71/* __ TIMER 0 */
72.equ TIM_MCR0, 0x600    /* Module configuration register */
73.equ TIM_IR0, 0x604     /* interrupt register */
74.equ TIM_CR0, 0x606     /* controle register */
75.equ TIM_SR0, 0x608     /* Status/prescaler register */
76.equ TIM_CNTR0, 0x60A   /* counter register */
77.equ TIM_PREL10, 0x60C  /* Preload register 1 */
78.equ TIM_PREL20, 0x60E  /* Preload register 2 */
79.equ TIM_COM0, 0x610    /* Compare register */
80
81/* __ TIMER 1 */
82
83.equ TIM_MCR1, 0x640    /* Module configuration register */
84.equ TIM_IR1, 0x644     /* interrupt register */
85.equ TIM_CR1, 0x646     /* controle register */
86.equ TIM_SR1, 0x648     /* Status/prescaler register */
87.equ TIM_CNTR1, 0x64A   /* counter register */ 
88.equ TIM_PREL11, 0x64C  /* Preload register 1 */       
89.equ TIM_PREL21, 0x64E  /* Preload register 2 */       
90.equ TIM_COM1, 0x650    /* Compare register */ 
91
92/* -- U.A.R.T.  equates -- */
93
94.equ UA_MCRH, 0x700     /* module configuration register */     
95.equ UA_MCRL, 0x701     /* module configuration register */     
96.equ UA_ILR, 0x704      /* Interrupt level */   
97.equ UA_IVR, 0x705      /* Interrupt vector */ 
98.equ UA_MR1A, 0x710     /* Mode register 1 A */
99.equ UA_MR2A, 0x720     /* Mode register 2 A*/ 
100.equ UA_CSRA, 0x711     /* Clock_select register A */   
101.equ UA_SRA, 0x711      /* status register A */
102.equ UA_CRA, 0x712      /* command register A */       
103.equ UA_RBA, 0x713      /* receive buffer A */ 
104.equ UA_TBA, 0x713      /* transmit buffer A */
105.equ UA_IPCR, 0x714     /* input port change register */       
106.equ UA_ACR, 0x714      /* auxiliary control register */       
107.equ UA_ISR, 0x715      /* interrupt status register */
108.equ UA_IER, 0x715      /* interrupt enable register */
109.equ UA_MR1B, 0x718     /* Mode register 1 B */
110.equ UA_MR2B, 0x721     /* Mode register  2 B */
111.equ UA_CSRB, 0x719     /* Clock_select register B */
112.equ UA_SRB, 0x719      /* status register B */
113.equ UA_CRB, 0x71A      /* command register A */
114.equ UA_RBB, 0x71B      /* receive buffer A */
115.equ UA_TBB, 0x71B      /* transmit buffer A */
116.equ UA_IP, 0x71D       /* Input port register */
117.equ UA_OPCR, 0x71D     /* output port control register */     
118.equ UA_OPS, 0x71E      /* output port bit set */       
119.equ UA_OPR, 0x71F      /* output port bit reset */
120.equ TX_A_EN, 0x01      /* Tx A irq enable */
121.equ TX_B_EN, 0x10      /* Tx B irq enable */
122.equ TX_A_DIS, 0xFE     /* Tx A irq enable */
123.equ TX_B_DIS, 0xEF     /* Tx B irq enable */
124.equ TX_AB_DIS, 0x22
125       
126/* -- DMA equates -- */
127.equ DMA_MCR0, 0x780    /* module configuration register */     
128.equ DMA_IR0, 0x784     /* Interrupt register */       
129.equ DMA_CCR0, 0x788    /* Channel control register */ 
130.equ DMA_CSR0, 0x78A    /* Channel status register */   
131.equ DMA_FCR0, 0x78B    /* Function code register */   
132.equ DMA_SARH0, 0x78C   /* Source adresse register */   
133.equ DMA_SARL0, 0x78E   /* Source adresse register */   
134.equ DMA_DARH0, 0x790   /* destination adresse register */     
135.equ DMA_DARL0, 0x792   /* destination adresse register */     
136.equ DMA_BTCH0, 0x794   /* byte transfer register */   
137.equ DMA_BTCL0, 0x796   /* byte transfer register */   
138.equ DMA_MCR1, 0x7A0    /* module configuration register */
139.equ DMA_IR1, 0x7A4     /* Interrupt register */       
140.equ DMA_CCR1, 0x7A8    /* Channel control register */ 
141.equ DMA_CSR1, 0x7AA    /* Channel status register */   
142.equ DMA_FCR1, 0x7AB    /* Function code register */   
143.equ DMA_SARH1, 0x7AC   /* Source adresse register */   
144.equ DMA_SARL1, 0x7AE   /* Source adresse register */   
145.equ DMA_DARH1, 0x7B0   /* destination adresse register */     
146.equ DMA_DARL1, 0x7B2   /* destination adresse register */     
147.equ DMA_BTCH1, 0x7B4   /* byte transfer register */   
148.equ DMA_BTCL1, 0x7B6   /* byte transfer register */   
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