[132f194] | 1 | /*---------------------------------------------------------------------------- |
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| 2 | * file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT |
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| 3 | * |
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| 4 | * MC68340 BCC Board Support Package |
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| 5 | * |
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| 6 | * date: 1/12/1993 |
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| 7 | * |
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| 8 | * Copyright 1989, Ready Systems FRANCE |
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| 9 | * |
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| 10 | * Supports: VRTX32 and RTscope |
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| 11 | * |
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| 12 | * Related Board: MOTOROLA BCC M68340 |
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| 13 | * |
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| 14 | * Description: EQUATES FOR 68340 DEVICES |
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| 15 | * |
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| 16 | * Changes: |
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| 17 | * - Geoffroy Montel (g_montel@yahoo.com) : |
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| 18 | * changed EQU syntax for GNU as |
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| 19 | * |
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| 20 | *----------------------------------------------------------------------------*/ |
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| 21 | |
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| 22 | /************************************************ |
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| 23 | * ATTENTION: must match defs. in C header file * |
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| 24 | ************************************************/ |
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| 25 | |
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| 26 | /* -- SIM equates -- system integration module */ |
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| 27 | .equ BASE_REG, 0x3FF00 |
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| 28 | .equ BASE_SIM, 0xEFFFF000 |
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| 29 | .equ SIM_MCR, 0x000 /* module configuration register */ |
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| 30 | .equ SIM_SYNCR, 0x004 /* clock synthesizer control register */ |
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| 31 | .equ SIM_AVR, 0x006 /* autovector register */ |
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| 32 | .equ SIM_RSR, 0x007 /* reset status register */ |
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| 33 | |
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| 34 | /* -- Port A -- */ |
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| 35 | .equ SIM_PORTA, 0x011 /* port A data */ |
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| 36 | .equ SIM_DDRA, 0x013 /* port A direction data */ |
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| 37 | .equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */ |
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| 38 | .equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */ |
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| 39 | |
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| 40 | /* -- Port B -- */ |
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| 41 | .equ SIM_PORTB, 0x019 /* port B data */ |
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| 42 | .equ SIM_PORTB1, 0x01B /* port B data auxiliary */ |
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| 43 | .equ SIM_DDRB, 0x01D /* port B direction data */ |
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| 44 | .equ SIM_PPRB, 0x01F /* Port B pin assignement */ |
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| 45 | .equ SIM_SWIV, 0x020 /* SW interrupt vector */ |
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| 46 | .equ SIM_SYPCR, 0x021 /* System protection control register */ |
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| 47 | .equ SIM_PICR, 0x022 /* Periodic interrupt control register */ |
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| 48 | .equ SIM_PITR, 0x024 /* Periodic interrupt timing register */ |
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| 49 | .equ SIM_SWSR, 0x027 /* Sofware service */ |
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| 50 | |
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| 51 | /* -- Chip select -- */ |
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| 52 | .equ SIM_MASKH0, 0x040 /* mask register CS0 */ |
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| 53 | .equ SIM_MASKL0, 0x042 /* mask register CS0 */ |
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| 54 | .equ SIM_ADDRH0, 0x044 /* base address CS0 */ |
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| 55 | .equ SIM_ADDRL0, 0x046 /* base address CS0 */ |
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| 56 | .equ SIM_MASKH1, 0x048 /* mask register CS1 */ |
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| 57 | .equ SIM_MASKL1, 0x04A /* mask register CS1 */ |
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| 58 | .equ SIM_ADDRH1, 0x04C /* base address CS1 */ |
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| 59 | .equ SIM_ADDRL1, 0x04E /* base address CS1 */ |
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| 60 | .equ SIM_MASKH2, 0x050 /* mask register CS2 */ |
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| 61 | .equ SIM_MASKL2, 0x052 /* mask register CS2 */ |
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| 62 | .equ SIM_ADDRH2, 0x054 /* base address CS2 */ |
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| 63 | .equ SIM_ADDRL2, 0x056 /* base address CS2 */ |
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| 64 | .equ SIM_MASKH3, 0x058 /* mask register CS3 */ |
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| 65 | .equ SIM_MASKL3, 0x05A /* mask register CS3 */ |
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| 66 | .equ SIM_ADDRH3, 0x05C /* base address CS3 */ |
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| 67 | .equ SIM_ADDRL3, 0x05E /* base address CS3 */ |
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| 68 | |
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| 69 | /* -- TIMERS equates -- */ |
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| 70 | |
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| 71 | /* __ TIMER 0 */ |
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| 72 | .equ TIM_MCR0, 0x600 /* Module configuration register */ |
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| 73 | .equ TIM_IR0, 0x604 /* interrupt register */ |
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| 74 | .equ TIM_CR0, 0x606 /* controle register */ |
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| 75 | .equ TIM_SR0, 0x608 /* Status/prescaler register */ |
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| 76 | .equ TIM_CNTR0, 0x60A /* counter register */ |
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| 77 | .equ TIM_PREL10, 0x60C /* Preload register 1 */ |
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| 78 | .equ TIM_PREL20, 0x60E /* Preload register 2 */ |
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| 79 | .equ TIM_COM0, 0x610 /* Compare register */ |
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| 80 | |
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| 81 | /* __ TIMER 1 */ |
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| 82 | |
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| 83 | .equ TIM_MCR1, 0x640 /* Module configuration register */ |
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| 84 | .equ TIM_IR1, 0x644 /* interrupt register */ |
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| 85 | .equ TIM_CR1, 0x646 /* controle register */ |
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| 86 | .equ TIM_SR1, 0x648 /* Status/prescaler register */ |
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| 87 | .equ TIM_CNTR1, 0x64A /* counter register */ |
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| 88 | .equ TIM_PREL11, 0x64C /* Preload register 1 */ |
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| 89 | .equ TIM_PREL21, 0x64E /* Preload register 2 */ |
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| 90 | .equ TIM_COM1, 0x650 /* Compare register */ |
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| 91 | |
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| 92 | /* -- U.A.R.T. equates -- */ |
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| 93 | |
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| 94 | .equ UA_MCRH, 0x700 /* module configuration register */ |
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| 95 | .equ UA_MCRL, 0x701 /* module configuration register */ |
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| 96 | .equ UA_ILR, 0x704 /* Interrupt level */ |
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| 97 | .equ UA_IVR, 0x705 /* Interrupt vector */ |
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| 98 | .equ UA_MR1A, 0x710 /* Mode register 1 A */ |
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| 99 | .equ UA_MR2A, 0x720 /* Mode register 2 A*/ |
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| 100 | .equ UA_CSRA, 0x711 /* Clock_select register A */ |
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| 101 | .equ UA_SRA, 0x711 /* status register A */ |
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| 102 | .equ UA_CRA, 0x712 /* command register A */ |
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| 103 | .equ UA_RBA, 0x713 /* receive buffer A */ |
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| 104 | .equ UA_TBA, 0x713 /* transmit buffer A */ |
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| 105 | .equ UA_IPCR, 0x714 /* input port change register */ |
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| 106 | .equ UA_ACR, 0x714 /* auxiliary control register */ |
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| 107 | .equ UA_ISR, 0x715 /* interrupt status register */ |
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| 108 | .equ UA_IER, 0x715 /* interrupt enable register */ |
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| 109 | .equ UA_MR1B, 0x718 /* Mode register 1 B */ |
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| 110 | .equ UA_MR2B, 0x721 /* Mode register 2 B */ |
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| 111 | .equ UA_CSRB, 0x719 /* Clock_select register B */ |
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| 112 | .equ UA_SRB, 0x719 /* status register B */ |
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| 113 | .equ UA_CRB, 0x71A /* command register A */ |
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| 114 | .equ UA_RBB, 0x71B /* receive buffer A */ |
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| 115 | .equ UA_TBB, 0x71B /* transmit buffer A */ |
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| 116 | .equ UA_IP, 0x71D /* Input port register */ |
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| 117 | .equ UA_OPCR, 0x71D /* output port control register */ |
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| 118 | .equ UA_OPS, 0x71E /* output port bit set */ |
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| 119 | .equ UA_OPR, 0x71F /* output port bit reset */ |
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| 120 | .equ TX_A_EN, 0x01 /* Tx A irq enable */ |
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| 121 | .equ TX_B_EN, 0x10 /* Tx B irq enable */ |
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| 122 | .equ TX_A_DIS, 0xFE /* Tx A irq enable */ |
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| 123 | .equ TX_B_DIS, 0xEF /* Tx B irq enable */ |
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| 124 | .equ TX_AB_DIS, 0x22 |
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| 125 | |
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| 126 | /* -- DMA equates -- */ |
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| 127 | .equ DMA_MCR0, 0x780 /* module configuration register */ |
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| 128 | .equ DMA_IR0, 0x784 /* Interrupt register */ |
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| 129 | .equ DMA_CCR0, 0x788 /* Channel control register */ |
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| 130 | .equ DMA_CSR0, 0x78A /* Channel status register */ |
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| 131 | .equ DMA_FCR0, 0x78B /* Function code register */ |
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| 132 | .equ DMA_SARH0, 0x78C /* Source adresse register */ |
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| 133 | .equ DMA_SARL0, 0x78E /* Source adresse register */ |
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| 134 | .equ DMA_DARH0, 0x790 /* destination adresse register */ |
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| 135 | .equ DMA_DARL0, 0x792 /* destination adresse register */ |
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| 136 | .equ DMA_BTCH0, 0x794 /* byte transfer register */ |
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| 137 | .equ DMA_BTCL0, 0x796 /* byte transfer register */ |
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| 138 | .equ DMA_MCR1, 0x7A0 /* module configuration register */ |
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| 139 | .equ DMA_IR1, 0x7A4 /* Interrupt register */ |
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| 140 | .equ DMA_CCR1, 0x7A8 /* Channel control register */ |
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| 141 | .equ DMA_CSR1, 0x7AA /* Channel status register */ |
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| 142 | .equ DMA_FCR1, 0x7AB /* Function code register */ |
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| 143 | .equ DMA_SARH1, 0x7AC /* Source adresse register */ |
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| 144 | .equ DMA_SARL1, 0x7AE /* Source adresse register */ |
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| 145 | .equ DMA_DARH1, 0x7B0 /* destination adresse register */ |
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| 146 | .equ DMA_DARL1, 0x7B2 /* destination adresse register */ |
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| 147 | .equ DMA_BTCH1, 0x7B4 /* byte transfer register */ |
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| 148 | .equ DMA_BTCL1, 0x7B6 /* byte transfer register */ |
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