source: rtems/bsps/m68k/csb360/start/init5272.c @ 9964895

5
Last change on this file since 9964895 was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 *  CSB360 hardware startup routines
3 *
4 *  This is where the real hardware setup is done. A minimal stack
5 *  has been provided by the start.S code. No normal C or RTEMS
6 *  functions can be called from here.
7 *
8 *  This initialization code based on hardware settings of dBUG
9 *  monitor. This must be changed if you like to run it immediately
10 *  after reset.
11 */
12
13/*
14 *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
15 *  Author: Victor V. Vengerov <vvv@oktet.ru>
16 *
17 *  Based on work:
18 *  Author:
19 *    David Fiddes, D.J@fiddes.surfaid.org
20 *    http://www.calm.hw.ac.uk/davidf/coldfire/
21 *
22 *  COPYRIGHT (c) 1989-1998.
23 *  On-Line Applications Research Corporation (OAR).
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.rtems.org/license/LICENSE.
28 */
29
30#include <bsp.h>
31#include <mcf5272/mcf5272.h>
32
33/* externs */
34extern void clear_bss(void);
35extern void start_csb360(void);
36extern void INTERRUPT_VECTOR(void);
37
38/* Set the pointers to the modules */
39sim_regs_t *g_sim_regs            = (void *) MCF5272_SIM_BASE(BSP_MBAR);
40intctrl_regs_t *g_intctrl_regs    = (void *) MCF5272_INT_BASE(BSP_MBAR);
41chipsel_regs_t *g_chipsel_regs    = (void *) MCF5272_CS_BASE(BSP_MBAR);
42gpio_regs_t *g_gpio_regs          = (void *) MCF5272_GPIO_BASE(BSP_MBAR);
43qspi_regs_t *g_qspi_regs          = (void *) MCF5272_QSPI_BASE(BSP_MBAR);
44pwm_regs_t *g_pwm_regs            = (void *) MCF5272_PWM_BASE(BSP_MBAR);
45dma_regs_t *g_dma_regs            = (void *) MCF5272_DMAC_BASE(BSP_MBAR);
46uart_regs_t *g_uart0_regs         = (void *) MCF5272_UART0_BASE(BSP_MBAR);
47uart_regs_t *g_uart1_regs         = (void *) MCF5272_UART1_BASE(BSP_MBAR);
48timer_regs_t *g_timer_regs        = (void *) MCF5272_TIMER_BASE(BSP_MBAR);
49plic_regs_t *g_plic_regs          = (void *) MCF5272_PLIC_BASE(BSP_MBAR);
50enet_regs_t *g_enet_regs          = (void *) MCF5272_ENET_BASE(BSP_MBAR);
51usb_regs_t *g_usb_regs            = (void *) MCF5272_USB_BASE(BSP_MBAR);
52
53#define m68k_set_srambar( _rambar0 ) \
54  __asm__ volatile (  "movec %0,%%rambar0\n\t" \
55                  "nop\n\t" \
56                  : : "d" (_rambar0) )
57
58#define m68k_set_mbar( _mbar ) \
59  __asm__ volatile (  "movec %0,%%mbar\n\t" \
60                  "nop\n\t" \
61                  : : "d" (_mbar) )
62
63#define mcf5272_enable_cache() \
64  m68k_set_cacr( MCF5272_CACR_CENB )
65
66
67#define mcf5272_disable_cache() \
68  __asm__ volatile (  "nop\n\t"    \
69                  "movec %0,%%cacr\n\t" \
70                  "nop\n\t" \
71                  "movec %0,%%cacr\n\t" \
72                  "nop\n\t" \
73                  : : "d" (MCF5272_CACR_CINV) )
74
75/*
76 * Initialize MCF5272 on-chip modules
77 */
78void init5272(void)
79{
80  /* Invalidate the cache - WARNING: It won't complete for 64 clocks */
81  m68k_set_cacr(MCF5272_CACR_CINV);
82
83  /* Set Module Base Address register */
84  m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
85
86  /* Set RAM Base Address register */
87  m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
88
89  /* Set System Control Register:
90   * Enet has highest priority, 16384 bus cycles before timeout
91   */
92  g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
93
94  /* System Protection Register:
95   * Enable Hardware watchdog timer.
96   */
97  g_sim_regs->spr = MCF5272_SPR_HWTEN;
98
99  /* Clear and mask all interrupts */
100  g_intctrl_regs->icr1 = 0x88888888;
101  g_intctrl_regs->icr2 = 0x88888888;
102  g_intctrl_regs->icr3 = 0x88888888;
103  g_intctrl_regs->icr4 = 0x88880000;
104
105  /* Copy the interrupt vector table to SRAM */
106  {
107    uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
108    uint32_t *intvec = (uint32_t *)BSP_RAMBAR;
109    register int i;
110    for (i = 0; i < 256; i++) {
111        *(intvec++) = *(inttab++);
112    }
113  }
114  m68k_set_vbr(BSP_RAMBAR);
115
116
117  /*
118   * Setup ACRs so that if cache turned on, periphal accesses
119   * are not messed up.  (Non-cacheable, serialized)
120   */
121  m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM)    |
122                MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM)    |
123                MCF5272_ACR_EN                          |
124                MCF5272_ACR_SM_ANY);
125
126/*
127  m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
128                 MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
129                 MCF5206E_ACR_EN                       |
130                 MCF5206E_ACR_SM_ANY);
131*/
132
133  /* Enable the caches */
134  m68k_set_cacr(MCF5272_CACR_CENB |
135                MCF5272_CACR_DCM);       /* Default is not cached */
136
137/*
138 * Copy data, clear BSS, switch stacks and call boot_card()
139 */
140/*
141CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
142*/
143  clear_bss();
144  start_csb360();
145
146}
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