Context Navigation

timerisr.S @ d7d66d7

Last change on this file since d7d66d7 was ddf3ea2, checked in by Sebastian Huber <sebastian.huber@…>, on 03/26/18 at 10:23:22

bsps/csb360: Move libcpu content to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

File size: 1.2 KB

Line
1	/**
2	* @file
3	* @brief Handle MCF5272 TIMER2 interrupts.
4	*
5	* All code in this routine is pure overhead which can perturb the
6	* accuracy of RTEMS' timing test suite.
7	*
8	* See also: benchmark_timer_read()
9	*
10	* To reduce overhead this is best to be the "rawest" hardware interupt
11	* handler you can write. This should be the only interrupt which can
12	* occur during the measured time period.
13	*
14	* An external counter, Timer_interrupts, is incremented.
15	*/
16
17	/*
18	* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
19	* Author: Victor V. Vengerov <vvv@oktet.ru>
20	*
21	* This file based on work:
22	* Author:
23	* David Fiddes, D.J@fiddes.surfaid.org
24	* http://www.calm.hw.ac.uk/davidf/coldfire/
25	*
26	* COPYRIGHT (c) 1989-1998.
27	* On-Line Applications Research Corporation (OAR).
28	*
29	* The license and distribution terms for this file may be
30	* found in the file LICENSE in this distribution or at
31	* http://www.rtems.org/license/LICENSE.
32	*/
33
34	#include <rtems/asm.h>
35	#include <bsp.h>
36
37	BEGIN_CODE
38	PUBLIC(timerisr)
39	SYM(timerisr):
40	move.l a0, a7@-
41	move.b # (MCF5272_TER_REF + MCF5272_TER_CAP), (a0)
42	addq.l #1,SYM(Timer_interrupts) \| increment timer value
43	move.l a7@+, a0
44	rte
45	END_CODE
46	END

Note: See TracBrowser for help on using the repository browser.