1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lm32_milkymist |
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5 | * |
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6 | * @brief System configuration. |
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7 | */ |
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8 | |
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9 | /* system_conf.h |
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10 | * Global System conf |
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11 | * |
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12 | * Milkymist port of RTEMS |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | * |
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18 | * COPYRIGHT (c) 2010, 2011 Sebastien Bourdeauducq |
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19 | */ |
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20 | |
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21 | #ifndef __SYSTEM_CONFIG_H_ |
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22 | #define __SYSTEM_CONFIG_H_ |
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23 | |
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24 | #define UART_BAUD_RATE (115200) |
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25 | |
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26 | /* Clock frequency */ |
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27 | #define MM_FREQUENCY (0xe0001074) |
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28 | |
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29 | /* FML bridge */ |
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30 | #define FMLBRG_FLUSH_BASE (0xc8000000) |
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31 | #define FMLBRG_LINE_LENGTH (32) |
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32 | #define FMLBRG_LINE_COUNT (512) |
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33 | |
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34 | /* UART */ |
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35 | #define MM_UART_RXTX (0xe0000000) |
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36 | #define MM_UART_DIV (0xe0000004) |
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37 | #define MM_UART_STAT (0xe0000008) |
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38 | #define MM_UART_CTRL (0xe000000c) |
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39 | |
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40 | #define UART_STAT_THRE (0x1) |
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41 | #define UART_STAT_RX_EVT (0x2) |
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42 | #define UART_STAT_TX_EVT (0x4) |
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43 | |
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44 | #define UART_CTRL_RX_INT (0x1) |
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45 | #define UART_CTRL_TX_INT (0x2) |
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46 | #define UART_CTRL_THRU (0x4) |
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47 | |
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48 | /* Timers */ |
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49 | #define MM_TIMER1_COMPARE (0xe0001024) |
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50 | #define MM_TIMER1_COUNTER (0xe0001028) |
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51 | #define MM_TIMER1_CONTROL (0xe0001020) |
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52 | |
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53 | #define MM_TIMER0_COMPARE (0xe0001014) |
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54 | #define MM_TIMER0_COUNTER (0xe0001018) |
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55 | #define MM_TIMER0_CONTROL (0xe0001010) |
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56 | |
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57 | #define TIMER_ENABLE (0x01) |
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58 | #define TIMER_AUTORESTART (0x02) |
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59 | |
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60 | /* GPIO */ |
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61 | #define MM_GPIO_IN (0xe0001000) |
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62 | #define MM_GPIO_OUT (0xe0001004) |
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63 | #define MM_GPIO_INTEN (0xe0001008) |
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64 | |
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65 | #define GPIO_BTN1 (0x00000001) |
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66 | #define GPIO_BTN2 (0x00000002) |
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67 | #define GPIO_BTN3 (0x00000004) |
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68 | #define GPIO_PCBREV0 (0x00000008) |
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69 | #define GPIO_PCBREV1 (0x00000010) |
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70 | #define GPIO_PCBREV2 (0x00000020) |
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71 | #define GPIO_PCBREV3 (0x00000040) |
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72 | #define GPIO_LED1 (0x00000001) |
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73 | #define GPIO_LED2 (0x00000002) |
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74 | |
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75 | /* System ID and reset */ |
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76 | #define MM_SYSTEM_ID (0xe000107c) |
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77 | |
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78 | /* ICAP */ |
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79 | #define MM_ICAP (0xe0001040) |
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80 | |
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81 | #define ICAP_READY (0x01) |
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82 | #define ICAP_CE (0x10000) |
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83 | #define ICAP_WRITE (0x20000) |
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84 | |
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85 | /* VGA */ |
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86 | #define MM_VGA_RESET (0xe0003000) |
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87 | |
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88 | #define MM_VGA_HRES (0xe0003004) |
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89 | #define MM_VGA_HSYNC_START (0xe0003008) |
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90 | #define MM_VGA_HSYNC_END (0xe000300C) |
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91 | #define MM_VGA_HSCAN (0xe0003010) |
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92 | |
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93 | #define MM_VGA_VRES (0xe0003014) |
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94 | #define MM_VGA_VSYNC_START (0xe0003018) |
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95 | #define MM_VGA_VSYNC_END (0xe000301C) |
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96 | #define MM_VGA_VSCAN (0xe0003020) |
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97 | |
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98 | #define MM_VGA_BASEADDRESS (0xe0003024) |
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99 | #define MM_VGA_BASEADDRESS_ACT (0xe0003028) |
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100 | |
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101 | #define MM_VGA_BURST_COUNT (0xe000302C) |
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102 | |
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103 | #define MM_VGA_DDC (0xe0003030) |
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104 | |
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105 | #define MM_VGA_CLKSEL (0xe0003034) |
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106 | |
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107 | #define VGA_RESET (0x01) |
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108 | #define VGA_DDC_SDAIN (0x1) |
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109 | #define VGA_DDC_SDAOUT (0x2) |
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110 | #define VGA_DDC_SDAOE (0x4) |
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111 | #define VGA_DDC_SDC (0x8) |
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112 | |
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113 | /* Ethernet */ |
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114 | #define MM_MINIMAC_SETUP (0xe0008000) |
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115 | #define MM_MINIMAC_MDIO (0xe0008004) |
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116 | |
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117 | #define MM_MINIMAC_STATE0 (0xe0008008) |
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118 | #define MM_MINIMAC_COUNT0 (0xe000800C) |
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119 | #define MM_MINIMAC_STATE1 (0xe0008010) |
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120 | #define MM_MINIMAC_COUNT1 (0xe0008014) |
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121 | |
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122 | #define MM_MINIMAC_TXCOUNT (0xe0008018) |
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123 | |
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124 | #define MINIMAC_RX0_BASE (0xb0000000) |
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125 | #define MINIMAC_RX1_BASE (0xb0000800) |
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126 | #define MINIMAC_TX_BASE (0xb0001000) |
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127 | |
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128 | #define MINIMAC_SETUP_PHYRST (0x1) |
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129 | |
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130 | #define MINIMAC_STATE_EMPTY (0x0) |
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131 | #define MINIMAC_STATE_LOADED (0x1) |
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132 | #define MINIMAC_STATE_PENDING (0x2) |
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133 | |
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134 | /* AC97 */ |
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135 | #define MM_AC97_CRCTL (0xe0005000) |
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136 | |
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137 | #define AC97_CRCTL_RQEN (0x01) |
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138 | #define AC97_CRCTL_WRITE (0x02) |
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139 | |
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140 | #define MM_AC97_CRADDR (0xe0005004) |
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141 | #define MM_AC97_CRDATAOUT (0xe0005008) |
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142 | #define MM_AC97_CRDATAIN (0xe000500C) |
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143 | |
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144 | #define MM_AC97_DCTL (0xe0005010) |
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145 | #define MM_AC97_DADDRESS (0xe0005014) |
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146 | #define MM_AC97_DREMAINING (0xe0005018) |
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147 | |
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148 | #define MM_AC97_UCTL (0xe0005020) |
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149 | #define MM_AC97_UADDRESS (0xe0005024) |
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150 | #define MM_AC97_UREMAINING (0xe0005028) |
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151 | |
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152 | #define AC97_SCTL_EN (0x01) |
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153 | |
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154 | #define AC97_MAX_DMASIZE (0x3fffc) |
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155 | |
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156 | /* SoftUSB */ |
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157 | #define MM_SOFTUSB_CONTROL (0xe000f000) |
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158 | |
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159 | #define SOFTUSB_CONTROL_RESET (0x1) |
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160 | |
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161 | #define MM_SOFTUSB_PMEM_BASE (0xa0000000) |
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162 | #define MM_SOFTUSB_DMEM_BASE (0xa0020000) |
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163 | |
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164 | #define SOFTUSB_PMEM_SIZE (1 << 13) |
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165 | #define SOFTUSB_DMEM_SIZE (1 << 13) |
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166 | |
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167 | /* PFPU */ |
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168 | #define MM_PFPU_CTL (0xe0006000) |
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169 | #define PFPU_CTL_START (0x01) |
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170 | #define PFPU_CTL_BUSY (0x01) |
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171 | |
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172 | #define MM_PFPU_MESHBASE (0xe0006004) |
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173 | #define MM_PFPU_HMESHLAST (0xe0006008) |
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174 | #define MM_PFPU_VMESHLAST (0xe000600C) |
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175 | |
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176 | #define MM_PFPU_CODEPAGE (0xe0006010) |
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177 | |
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178 | #define MM_PFPU_DREGBASE (0xe0006400) |
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179 | #define MM_PFPU_CODEBASE (0xe0006800) |
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180 | |
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181 | #define PFPU_PAGESIZE (512) |
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182 | #define PFPU_SPREG_COUNT (2) |
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183 | #define PFPU_REG_X (0) |
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184 | #define PFPU_REG_Y (1) |
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185 | |
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186 | /* TMU */ |
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187 | #define MM_TMU_CTL (0xe0007000) |
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188 | #define TMU_CTL_START (0x01) |
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189 | #define TMU_CTL_BUSY (0x01) |
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190 | #define TMU_CTL_CHROMAKEY (0x02) |
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191 | |
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192 | #define MM_TMU_HMESHLAST (0xe0007004) |
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193 | #define MM_TMU_VMESHLAST (0xe0007008) |
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194 | #define MM_TMU_BRIGHTNESS (0xe000700C) |
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195 | #define MM_TMU_CHROMAKEY (0xe0007010) |
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196 | |
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197 | #define MM_TMU_VERTICESADR (0xe0007014) |
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198 | #define MM_TMU_TEXFBUF (0xe0007018) |
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199 | #define MM_TMU_TEXHRES (0xe000701C) |
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200 | #define MM_TMU_TEXVRES (0xe0007020) |
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201 | #define MM_TMU_TEXHMASK (0xe0007024) |
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202 | #define MM_TMU_TEXVMASK (0xe0007028) |
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203 | |
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204 | #define MM_TMU_DSTFBUF (0xe000702C) |
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205 | #define MM_TMU_DSTHRES (0xe0007030) |
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206 | #define MM_TMU_DSTVRES (0xe0007034) |
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207 | #define MM_TMU_DSTHOFFSET (0xe0007038) |
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208 | #define MM_TMU_DSTVOFFSET (0xe000703C) |
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209 | #define MM_TMU_DSTSQUAREW (0xe0007040) |
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210 | #define MM_TMU_DSTSQUAREH (0xe0007044) |
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211 | |
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212 | #define MM_TMU_ALPHA (0xe0007048) |
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213 | |
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214 | /* Memory card */ |
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215 | #define MM_MEMCARD_CLK2XDIV (0xe0004000) |
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216 | |
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217 | #define MM_MEMCARD_ENABLE (0xe0004004) |
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218 | |
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219 | #define MEMCARD_ENABLE_CMD_TX (0x1) |
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220 | #define MEMCARD_ENABLE_CMD_RX (0x2) |
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221 | #define MEMCARD_ENABLE_DAT_TX (0x4) |
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222 | #define MEMCARD_ENABLE_DAT_RX (0x8) |
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223 | |
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224 | #define MM_MEMCARD_PENDING (0xe0004008) |
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225 | |
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226 | #define MEMCARD_PENDING_CMD_TX (0x1) |
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227 | #define MEMCARD_PENDING_CMD_RX (0x2) |
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228 | #define MEMCARD_PENDING_DAT_TX (0x4) |
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229 | #define MEMCARD_PENDING_DAT_RX (0x8) |
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230 | |
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231 | #define MM_MEMCARD_START (0xe000400c) |
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232 | |
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233 | #define MEMCARD_START_CMD_RX (0x1) |
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234 | #define MEMCARD_START_DAT_RX (0x2) |
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235 | |
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236 | #define MM_MEMCARD_CMD (0xe0004010) |
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237 | #define MM_MEMCARD_DAT (0xe0004014) |
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238 | |
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239 | /* DMX */ |
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240 | #define MM_DMX_TX(x) (0xe000c000+4*(x)) |
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241 | #define MM_DMX_THRU (0xe000c800) |
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242 | #define MM_DMX_RX(x) (0xe000d000+4*(x)) |
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243 | |
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244 | /* MIDI */ |
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245 | #define MM_MIDI_RXTX (0xe000b000) |
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246 | #define MM_MIDI_DIV (0xe000b004) |
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247 | #define MM_MIDI_STAT (0xe000b008) |
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248 | #define MM_MIDI_CTRL (0xe000b00c) |
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249 | |
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250 | #define MIDI_STAT_THRE (0x1) |
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251 | #define MIDI_STAT_RX_EVT (0x2) |
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252 | #define MIDI_STAT_TX_EVT (0x4) |
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253 | |
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254 | #define MIDI_CTRL_RX_INT (0x1) |
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255 | #define MIDI_CTRL_TX_INT (0x2) |
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256 | #define MIDI_CTRL_THRU (0x4) |
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257 | |
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258 | /* IR */ |
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259 | #define MM_IR_RX (0xe000e000) |
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260 | |
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261 | /* Video input */ |
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262 | #define MM_BT656_I2C (0xe000a000) |
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263 | #define MM_BT656_FILTERSTATUS (0xe000a004) |
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264 | #define MM_BT656_BASE (0xe000a008) |
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265 | #define MM_BT656_MAXBURSTS (0xe000a00c) |
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266 | #define MM_BT656_DONEBURSTS (0xe000a010) |
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267 | |
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268 | #define BT656_I2C_SDAIN (0x1) |
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269 | #define BT656_I2C_SDAOUT (0x2) |
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270 | #define BT656_I2C_SDAOE (0x4) |
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271 | #define BT656_I2C_SDC (0x8) |
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272 | |
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273 | #define BT656_FILTER_FIELD1 (0x1) |
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274 | #define BT656_FILTER_FIELD2 (0x2) |
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275 | #define BT656_FILTER_INFRAME (0x4) |
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276 | |
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277 | /* Interrupts */ |
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278 | #define MM_IRQ_UART (0) |
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279 | #define MM_IRQ_GPIO (1) |
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280 | #define MM_IRQ_TIMER0 (2) |
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281 | #define MM_IRQ_TIMER1 (3) |
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282 | #define MM_IRQ_AC97CRREQUEST (4) |
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283 | #define MM_IRQ_AC97CRREPLY (5) |
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284 | #define MM_IRQ_AC97DMAR (6) |
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285 | #define MM_IRQ_AC97DMAW (7) |
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286 | #define MM_IRQ_PFPU (8) |
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287 | #define MM_IRQ_TMU (9) |
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288 | #define MM_IRQ_ETHRX (10) |
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289 | #define MM_IRQ_ETHTX (11) |
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290 | #define MM_IRQ_VIDEOIN (12) |
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291 | #define MM_IRQ_MIDI (13) |
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292 | #define MM_IRQ_IR (14) |
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293 | #define MM_IRQ_USB (15) |
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294 | |
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295 | /* Flash layout */ |
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296 | #define FLASH_BASE (0x80000000) |
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297 | |
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298 | #define FLASH_OFFSET_STANDBY_BITSTREAM (0x80000000) |
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299 | |
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300 | #define FLASH_OFFSET_RESCUE_BITSTREAM (0x800A0000) |
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301 | #define FLASH_OFFSET_RESCUE_BIOS (0x80220000) |
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302 | #define FLASH_OFFSET_MAC_ADDRESS (0x802200E0) |
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303 | #define FLASH_OFFSET_RESCUE_SPLASH (0x80240000) |
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304 | #define FLASH_OFFSET_RESCUE_APP (0x802E0000) |
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305 | |
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306 | #define FLASH_OFFSET_REGULAR_BITSTREAM (0x806E0000) |
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307 | #define FLASH_OFFSET_REGULAR_BIOS (0x80860000) |
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308 | #define FLASH_OFFSET_REGULAR_SPLASH (0x80880000) |
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309 | #define FLASH_OFFSET_REGULAR_APP (0x80920000) |
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310 | |
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311 | /* MMIO */ |
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312 | #define MM_READ(reg) (*((volatile unsigned int *)(reg))) |
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313 | #define MM_WRITE(reg, val) *((volatile unsigned int *)(reg)) = val |
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314 | |
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315 | /* Flash partitions */ |
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316 | |
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317 | #define FLASH_SECTOR_SIZE (128*1024) |
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318 | |
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319 | #define FLASH_PARTITION_COUNT (5) |
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320 | |
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321 | #define FLASH_PARTITIONS { \ |
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322 | { .start_address = 0x806E0000, .length = 0x0180000 }, \ |
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323 | { .start_address = 0x80860000, .length = 0x0020000 }, \ |
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324 | { .start_address = 0x80880000, .length = 0x00A0000 }, \ |
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325 | { .start_address = 0x80920000, .length = 0x0400000 }, \ |
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326 | { .start_address = 0x80D20000, .length = 0x12E0000 }, \ |
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327 | } |
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328 | |
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329 | #endif /* __SYSTEM_CONFIG_H_ */ |
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