1 | /* |
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2 | * Copyright (C) 2017 Cobham Gaisler AB |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #ifndef GRLIB_IMPL_H |
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10 | #define GRLIB_IMPL_H |
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11 | |
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12 | #include <rtems/score/basedefs.h> |
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13 | #include <rtems/malloc.h> |
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14 | |
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15 | /* |
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16 | * Use interrupt lock primitives compatible with SMP defined in RTEMS 4.11.99 |
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17 | * and higher. |
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18 | */ |
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19 | #if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x040b63) |
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20 | |
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21 | #include <rtems/score/isrlock.h> |
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22 | |
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23 | /* map via rtems_interrupt_lock_* API: */ |
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24 | #define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock) |
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25 | #define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name) |
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26 | #define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level) |
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27 | #define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level) |
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28 | #define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level) |
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29 | #define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level) |
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30 | #define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k |
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31 | #define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k) |
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32 | #define SPIN_FREE(lock) rtems_interrupt_lock_destroy(lock) |
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33 | |
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34 | /* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */ |
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35 | #define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level |
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36 | #define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_local_disable(_level) |
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37 | #define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_local_enable(_level) |
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38 | |
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39 | #else |
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40 | |
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41 | #ifdef RTEMS_SMP |
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42 | #error SMP mode not compatible with these interrupt lock primitives |
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43 | #endif |
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44 | |
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45 | /* maintain single-core compatibility with older versions of RTEMS: */ |
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46 | #define SPIN_DECLARE(name) |
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47 | #define SPIN_INIT(lock, name) |
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48 | #define SPIN_LOCK(lock, level) |
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49 | #define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level) |
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50 | #define SPIN_UNLOCK(lock, level) |
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51 | #define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level) |
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52 | #define SPIN_IRQFLAGS(k) rtems_interrupt_level k |
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53 | #define SPIN_ISR_IRQFLAGS(k) |
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54 | #define SPIN_FREE(lock) |
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55 | |
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56 | /* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */ |
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57 | #define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level |
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58 | #define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_disable(_level) |
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59 | #define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_enable(_level) |
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60 | |
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61 | #endif |
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62 | |
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63 | #ifdef __cplusplus |
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64 | extern "C" { |
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65 | #endif |
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66 | |
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67 | #if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000) |
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68 | |
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69 | RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size) |
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70 | { |
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71 | return rtems_malloc(size); |
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72 | } |
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73 | |
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74 | RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize) |
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75 | { |
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76 | return rtems_calloc(nelem, elsize); |
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77 | } |
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78 | |
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79 | #else |
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80 | |
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81 | RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size) |
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82 | { |
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83 | return malloc(size); |
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84 | } |
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85 | |
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86 | RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize) |
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87 | { |
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88 | return calloc(nelem, elsize); |
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89 | } |
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90 | |
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91 | #endif |
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92 | |
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93 | #ifdef __sparc__ |
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94 | |
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95 | RTEMS_INLINE_ROUTINE unsigned char grlib_read_uncached8(unsigned int address) |
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96 | { |
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97 | unsigned char tmp; |
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98 | __asm__ (" lduba [%1]1, %0 " |
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99 | : "=r"(tmp) |
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100 | : "r"(address) |
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101 | ); |
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102 | return tmp; |
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103 | } |
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104 | |
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105 | RTEMS_INLINE_ROUTINE unsigned short grlib_read_uncached16(unsigned int addr) { |
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106 | unsigned short tmp; |
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107 | __asm__ (" lduha [%1]1, %0 " |
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108 | : "=r"(tmp) |
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109 | : "r"(addr) |
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110 | ); |
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111 | return tmp; |
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112 | } |
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113 | |
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114 | |
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115 | RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address) |
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116 | { |
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117 | unsigned int tmp; |
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118 | __asm__ (" lda [%1]1, %0 " |
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119 | : "=r"(tmp) |
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120 | : "r"(address) |
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121 | ); |
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122 | return tmp; |
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123 | } |
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124 | |
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125 | #define GRLIB_DMA_IS_CACHE_COHERENT CPU_SPARC_HAS_SNOOPING |
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126 | |
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127 | #else |
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128 | |
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129 | static unsigned char __inline__ grlib_read_uncached8(unsigned int address) |
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130 | { |
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131 | unsigned char tmp = (*(volatile unsigned char *)(address)); |
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132 | return tmp; |
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133 | } |
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134 | |
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135 | static __inline__ unsigned short grlib_read_uncached16(unsigned int address) { |
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136 | unsigned short tmp = (*(volatile unsigned short *)(address)); |
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137 | return tmp; |
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138 | } |
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139 | |
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140 | RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address) |
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141 | { |
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142 | unsigned int tmp = (*(volatile unsigned int *)(address)); |
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143 | return tmp; |
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144 | } |
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145 | |
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146 | #define GRLIB_DMA_IS_CACHE_COHERENT 1 |
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147 | |
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148 | #endif |
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149 | |
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150 | extern struct ambapp_bus ambapp_plb; |
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151 | |
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152 | #ifdef __cplusplus |
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153 | } |
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154 | #endif |
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155 | |
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156 | #endif /* GRLIB_IMPL_H */ |
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