1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* |
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4 | * Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR) |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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25 | * POSSIBILITY OF SUCH DAMAGE. |
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26 | */ |
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27 | |
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28 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H |
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29 | #define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H |
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30 | |
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31 | #include <bsp/utility.h> |
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32 | |
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33 | typedef struct { |
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34 | uint32_t config; |
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35 | #define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17) |
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36 | #define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16) |
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37 | #define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15) |
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38 | #define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14) |
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39 | #define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13) |
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40 | #define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13) |
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41 | #define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) |
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42 | #define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9) |
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43 | #define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8) |
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44 | #define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5) |
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45 | #define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5) |
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46 | #define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) |
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47 | #define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2) |
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48 | #define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1) |
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49 | #define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0) |
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50 | uint32_t irqstatus; |
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51 | uint32_t irqenable; |
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52 | uint32_t irqdisable; |
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53 | uint32_t irqmask; |
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54 | #define CADENCE_SPI_IXR_TXUF BSP_BIT32(6) |
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55 | #define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5) |
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56 | #define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4) |
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57 | #define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3) |
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58 | #define CADENCE_SPI_IXR_TXOW BSP_BIT32(2) |
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59 | #define CADENCE_SPI_IXR_MODF BSP_BIT32(1) |
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60 | #define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0) |
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61 | uint32_t spienable; |
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62 | #define CADENCE_SPI_EN BSP_BIT32(0) |
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63 | uint32_t delay; |
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64 | #define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31) |
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65 | #define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31) |
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66 | #define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) |
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67 | #define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23) |
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68 | #define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23) |
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69 | #define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) |
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70 | #define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15) |
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71 | #define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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72 | #define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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73 | #define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7) |
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74 | #define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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75 | #define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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76 | uint32_t txdata; |
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77 | uint32_t rxdata; |
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78 | uint32_t slave_idle_count; |
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79 | uint32_t txthreshold; |
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80 | uint32_t rxthreshold; |
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81 | uint32_t moduleid; |
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82 | } cadence_spi; |
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83 | |
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84 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */ |
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