1 | /* |
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2 | * This file contains the implementation of the function described in irq.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2009 embedded brains GmbH |
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7 | * Copyright (C) 1998 valette@crf.canon.fr |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #include <bsp.h> |
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15 | #include <bsp/irq.h> |
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16 | #include <bsp/irq-generic.h> |
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17 | #include <rtems/score/cpu.h> |
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18 | |
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19 | #include <stdlib.h> |
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20 | #include <stdio.h> |
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21 | #include <inttypes.h> |
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22 | |
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23 | |
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24 | #include "elcr.h" |
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25 | |
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26 | RTEMS_INTERRUPT_LOCK_DEFINE( static, rtems_i8259_access_lock, "rtems_i8259_access_lock" ); |
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27 | |
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28 | /* |
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29 | * pointer to the mask representing the additionnal irq vectors |
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30 | * that must be disabled when a particular entry is activated. |
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31 | * They will be dynamically computed from teh prioruty table given |
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32 | * in BSP_rtems_irq_mngt_set(); |
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33 | * CAUTION : this table is accessed directly by interrupt routine |
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34 | * prologue. |
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35 | */ |
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36 | static rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER]; |
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37 | |
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38 | /* |
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39 | * Stats of interrupts dispatched. |
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40 | */ |
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41 | static uint32_t irq_count[BSP_IRQ_VECTOR_NUMBER] = {0}; |
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42 | static uint32_t spurious_count; |
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43 | |
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44 | /* |
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45 | * Edge or level trigger interrupts. |
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46 | */ |
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47 | static enum intr_trigger irq_trigger[BSP_IRQ_LINES_NUMBER]; |
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48 | |
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49 | /*-------------------------------------------------------------------------+ |
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50 | | Cache for 1st and 2nd PIC IRQ line's mssk (enabled or disabled) register. |
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51 | +--------------------------------------------------------------------------*/ |
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52 | /* |
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53 | * lower byte is interrupt mask on the master PIC. |
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54 | * while upper bits are interrupt on the slave PIC. |
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55 | * This cache is initialized in ldseg.s |
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56 | */ |
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57 | static rtems_i8259_masks i8259a_imr_cache = 0xFFFB; |
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58 | static rtems_i8259_masks i8259a_in_progress = 0; |
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59 | |
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60 | static inline |
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61 | void BSP_i8259a_irq_update_master_imr( void ) |
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62 | { |
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63 | rtems_i8259_masks mask = i8259a_in_progress | i8259a_imr_cache; |
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64 | outport_byte( PIC_MASTER_IMR_IO_PORT, mask & 0xff ); |
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65 | } |
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66 | |
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67 | static inline |
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68 | void BSP_i8259a_irq_update_slave_imr( void ) |
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69 | { |
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70 | rtems_i8259_masks mask = i8259a_in_progress | i8259a_imr_cache; |
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71 | outport_byte( PIC_SLAVE_IMR_IO_PORT, ( mask >> 8 ) & 0xff ); |
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72 | } |
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73 | |
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74 | /* |
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75 | * Print the stats. |
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76 | */ |
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77 | uint32_t BSP_irq_count_dump(FILE *f) |
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78 | { |
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79 | uint32_t tot = 0; |
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80 | int i; |
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81 | if ( !f ) |
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82 | f = stdout; |
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83 | fprintf(f,"SPURIOUS: %9"PRIu32"\n", spurious_count); |
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84 | for ( i = 0; i < BSP_IRQ_VECTOR_NUMBER; i++ ) { |
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85 | char type = '-'; |
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86 | if (i < BSP_IRQ_LINES_NUMBER) |
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87 | type = irq_trigger[i] == INTR_TRIGGER_EDGE ? 'E' : 'L'; |
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88 | tot += irq_count[i]; |
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89 | fprintf(f,"IRQ %2u: %c %9"PRIu32"\n", i, type, irq_count[i]); |
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90 | } |
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91 | return tot; |
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92 | } |
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93 | |
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94 | /* |
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95 | * Is the IRQ valid? |
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96 | */ |
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97 | static inline bool BSP_i8259a_irq_valid(const rtems_irq_number irqLine) |
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98 | { |
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99 | return ((int)irqLine >= BSP_IRQ_VECTOR_LOWEST_OFFSET) && |
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100 | ((int)irqLine <= BSP_IRQ_MAX_ON_i8259A); |
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101 | } |
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102 | |
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103 | /* |
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104 | * Read the IRR register. The default. |
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105 | */ |
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106 | static inline uint8_t BSP_i8259a_irq_int_request_reg(uint32_t ioport) |
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107 | { |
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108 | uint8_t isr; |
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109 | inport_byte(ioport, isr); |
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110 | return isr; |
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111 | } |
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112 | |
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113 | /* |
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114 | * Read the ISR register. Keep the default of the IRR. |
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115 | */ |
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116 | static inline uint8_t BSP_i8259a_irq_in_service_reg(uint32_t ioport) |
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117 | { |
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118 | uint8_t isr; |
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119 | outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR | PIC_OCW3_RIS); |
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120 | inport_byte(ioport, isr); |
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121 | outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR); |
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122 | return isr; |
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123 | } |
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124 | |
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125 | /*-------------------------------------------------------------------------+ |
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126 | | Function: BSP_irq_disable_at_i8259a |
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127 | | Description: Mask IRQ line in appropriate PIC chip. |
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128 | | Global Variables: i8259a_imr_cache, i8259a_in_progress |
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129 | | Arguments: vector_offset - number of IRQ line to mask. |
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130 | | Returns: 0 is OK. |
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131 | +--------------------------------------------------------------------------*/ |
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132 | static int BSP_irq_disable_at_i8259a(const rtems_irq_number irqLine) |
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133 | { |
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134 | unsigned short mask; |
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135 | rtems_interrupt_lock_context lock_context; |
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136 | |
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137 | rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context); |
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138 | |
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139 | mask = 1 << irqLine; |
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140 | i8259a_imr_cache |= mask; |
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141 | |
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142 | if (irqLine < 8) |
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143 | { |
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144 | BSP_i8259a_irq_update_master_imr(); |
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145 | } |
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146 | else |
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147 | { |
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148 | BSP_i8259a_irq_update_slave_imr(); |
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149 | } |
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150 | |
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151 | rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context); |
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152 | |
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153 | return 0; |
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154 | } |
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155 | |
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156 | /*-------------------------------------------------------------------------+ |
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157 | | Function: BSP_irq_enable_at_i8259a |
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158 | | Description: Unmask IRQ line in appropriate PIC chip. |
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159 | | Global Variables: i8259a_imr_cache, i8259a_in_progress |
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160 | | Arguments: irqLine - number of IRQ line to mask. |
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161 | | Returns: Nothing. |
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162 | +--------------------------------------------------------------------------*/ |
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163 | static int BSP_irq_enable_at_i8259a(const rtems_irq_number irqLine) |
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164 | { |
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165 | unsigned short mask; |
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166 | rtems_interrupt_lock_context lock_context; |
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167 | uint8_t isr; |
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168 | uint8_t irr; |
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169 | |
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170 | rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context); |
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171 | |
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172 | mask = 1 << irqLine; |
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173 | i8259a_imr_cache &= ~mask; |
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174 | |
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175 | if (irqLine < 8) |
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176 | { |
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177 | isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT); |
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178 | irr = BSP_i8259a_irq_int_request_reg(PIC_MASTER_COMMAND_IO_PORT); |
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179 | BSP_i8259a_irq_update_master_imr(); |
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180 | } |
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181 | else |
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182 | { |
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183 | isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT); |
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184 | irr = BSP_i8259a_irq_int_request_reg(PIC_SLAVE_COMMAND_IO_PORT); |
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185 | BSP_i8259a_irq_update_slave_imr(); |
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186 | } |
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187 | |
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188 | if (((isr ^ irr) & mask) != 0) |
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189 | printk("i386: isr=%x irr=%x\n", isr, irr); |
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190 | |
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191 | rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context); |
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192 | |
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193 | return 0; |
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194 | } /* mask_irq */ |
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195 | |
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196 | /*-------------------------------------------------------------------------+ |
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197 | | Function: BSP_irq_ack_at_i8259a |
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198 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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199 | | Global Variables: None. |
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200 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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201 | | Returns: Nothing. |
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202 | +--------------------------------------------------------------------------*/ |
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203 | static int BSP_irq_ack_at_i8259a(const rtems_irq_number irqLine) |
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204 | { |
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205 | uint8_t slave_isr = 0; |
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206 | |
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207 | if (irqLine >= 8) { |
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208 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); |
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209 | slave_isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT); |
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210 | } |
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211 | |
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212 | /* |
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213 | * Only issue the EOI to the master if there are no more interrupts in |
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214 | * service for the slave. i8259a data sheet page 18, The Special Fully Nested |
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215 | * Mode, b. |
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216 | */ |
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217 | if (slave_isr == 0) |
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218 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); |
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219 | |
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220 | return 0; |
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221 | |
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222 | } /* ackIRQ */ |
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223 | |
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224 | /* |
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225 | * ------------------------ RTEMS Irq helper functions ---------------- |
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226 | */ |
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227 | |
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228 | static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={ |
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229 | /* |
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230 | * actual priorities for each interrupt source: |
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231 | * 0 means that only current interrupt is masked |
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232 | * 255 means all other interrupts are masked |
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233 | * The second entry has a priority of 255 because |
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234 | * it is the slave pic entry and is should always remain |
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235 | * unmasked. |
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236 | */ |
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237 | 0,0, |
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238 | 255, |
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239 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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240 | }; |
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241 | |
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242 | static void compute_i8259_masks_from_prio (void) |
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243 | { |
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244 | rtems_interrupt_lock_context lock_context; |
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245 | unsigned int i; |
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246 | unsigned int j; |
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247 | |
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248 | rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context); |
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249 | |
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250 | /* |
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251 | * Always mask at least current interrupt to prevent re-entrance |
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252 | */ |
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253 | for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) { |
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254 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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255 | for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) { |
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256 | /* |
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257 | * Mask interrupts at i8259 level that have a lower priority |
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258 | */ |
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259 | if (irqPrioTable [i] > irqPrioTable [j]) { |
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260 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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261 | } |
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262 | } |
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263 | } |
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264 | |
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265 | rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context); |
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266 | } |
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267 | |
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268 | static inline bool bsp_interrupt_vector_is_valid(rtems_vector_number vector) |
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269 | { |
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270 | return BSP_i8259a_irq_valid((const rtems_irq_number) vector); |
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271 | } |
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272 | |
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273 | rtems_status_code bsp_interrupt_get_attributes( |
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274 | rtems_vector_number vector, |
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275 | rtems_interrupt_attributes *attributes |
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276 | ) |
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277 | { |
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278 | return RTEMS_SUCCESSFUL; |
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279 | } |
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280 | |
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281 | rtems_status_code bsp_interrupt_is_pending( |
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282 | rtems_vector_number vector, |
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283 | bool *pending |
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284 | ) |
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285 | { |
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286 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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287 | bsp_interrupt_assert(pending != NULL); |
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288 | *pending = false; |
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289 | return RTEMS_UNSATISFIED; |
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290 | } |
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291 | |
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292 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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293 | { |
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294 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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295 | return RTEMS_UNSATISFIED; |
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296 | } |
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297 | |
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298 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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299 | { |
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300 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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301 | return RTEMS_UNSATISFIED; |
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302 | } |
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303 | |
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304 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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305 | rtems_vector_number vector, |
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306 | bool *enabled |
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307 | ) |
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308 | { |
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309 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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310 | bsp_interrupt_assert(enabled != NULL); |
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311 | *enabled = false; |
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312 | return RTEMS_UNSATISFIED; |
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313 | } |
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314 | |
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315 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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316 | { |
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317 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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318 | BSP_irq_enable_at_i8259a(vector); |
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319 | return RTEMS_SUCCESSFUL; |
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320 | } |
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321 | |
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322 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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323 | { |
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324 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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325 | BSP_irq_disable_at_i8259a(vector); |
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326 | return RTEMS_SUCCESSFUL; |
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327 | } |
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328 | |
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329 | void bsp_interrupt_facility_initialize(void) |
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330 | { |
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331 | int i; |
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332 | |
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333 | /* |
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334 | * set up internal tables used by rtems interrupt prologue |
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335 | */ |
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336 | compute_i8259_masks_from_prio(); |
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337 | |
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338 | /* |
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339 | * must enable slave pic anyway |
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340 | */ |
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341 | BSP_irq_enable_at_i8259a(2); |
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342 | |
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343 | /* |
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344 | * Probe the ELCR. |
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345 | */ |
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346 | elcr_probe(); |
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347 | |
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348 | for (i = 0; i < BSP_IRQ_LINES_NUMBER; i++) |
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349 | irq_trigger[i] = elcr_read_trigger(i); |
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350 | } |
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351 | |
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352 | static bool bsp_interrupt_handler_is_empty(rtems_vector_number vector) |
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353 | { |
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354 | return bsp_interrupt_entry_load_first(vector) == NULL; |
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355 | } |
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356 | |
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357 | /* |
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358 | * Global so the asm handler can call it. |
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359 | */ |
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360 | void BSP_dispatch_isr(int vector); |
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361 | |
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362 | void BSP_dispatch_isr(int vector) |
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363 | { |
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364 | rtems_interrupt_lock_context lock_context; |
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365 | rtems_i8259_masks in_progress_save = 0; |
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366 | |
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367 | if (vector < BSP_IRQ_VECTOR_NUMBER) { |
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368 | /* |
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369 | * Hardware? |
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370 | */ |
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371 | if (vector <= BSP_IRQ_MAX_ON_i8259A) { |
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372 | |
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373 | rtems_interrupt_lock_acquire_isr(&rtems_i8259_access_lock, &lock_context); |
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374 | |
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375 | /* |
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376 | * See if this is a spurious interrupt. |
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377 | */ |
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378 | if ((vector == 7 || vector == 15)) { |
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379 | /* |
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380 | * Only check it there no handler for 7 or 15. |
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381 | */ |
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382 | if (bsp_interrupt_handler_is_empty(vector)) { |
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383 | /* |
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384 | * Read the ISR register to see if IRQ 7/15 is really pending. |
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385 | */ |
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386 | uint8_t isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT); |
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387 | if ((isr & (1 << 7)) == 0) { |
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388 | ++spurious_count; |
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389 | rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context); |
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390 | return; |
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391 | } |
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392 | } |
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393 | } |
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394 | |
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395 | /* |
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396 | * Save the current cached value for the IMR. It will have the bit for this |
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397 | * vector clear. |
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398 | */ |
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399 | if (vector <= BSP_IRQ_MAX_ON_i8259A) { |
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400 | in_progress_save = i8259a_in_progress; |
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401 | i8259a_in_progress |= irq_mask_or_tbl[vector]; |
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402 | BSP_i8259a_irq_update_master_imr(); |
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403 | BSP_i8259a_irq_update_slave_imr(); |
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404 | } |
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405 | |
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406 | /* |
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407 | * Do not use auto-EOI as some slave PIC do not work correctly. |
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408 | */ |
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409 | BSP_irq_ack_at_i8259a(vector); |
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410 | |
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411 | rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context); |
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412 | } |
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413 | |
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414 | /* |
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415 | * Count the interrupt. |
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416 | */ |
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417 | irq_count[vector]++; |
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418 | |
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419 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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420 | /* |
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421 | * Allow nesting. |
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422 | */ |
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423 | __asm__ __volatile__("sti"); |
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424 | |
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425 | bsp_interrupt_handler_dispatch(vector); |
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426 | |
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427 | /* |
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428 | * Disallow nesting. |
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429 | */ |
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430 | __asm__ __volatile__("cli"); |
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431 | |
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432 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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433 | |
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434 | if (vector <= BSP_IRQ_MAX_ON_i8259A) { |
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435 | |
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436 | rtems_interrupt_lock_acquire_isr(&rtems_i8259_access_lock, &lock_context); |
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437 | |
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438 | /* |
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439 | * Put the mask back but keep this vector masked if the trigger type is |
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440 | * level. The driver or a thread level interrupt server needs to enable it |
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441 | * again. |
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442 | */ |
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443 | if (vector <= BSP_IRQ_MAX_ON_i8259A) { |
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444 | i8259a_in_progress = in_progress_save; |
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445 | BSP_i8259a_irq_update_master_imr(); |
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446 | BSP_i8259a_irq_update_slave_imr(); |
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447 | } |
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448 | |
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449 | rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context); |
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450 | } |
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451 | } |
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452 | } |
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