source: rtems/bsps/i386/shared/cache/cache.c @ 4cf93658

Last change on this file since 4cf93658 was 4cf93658, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 27, 2018 at 1:37:51 PM

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 *  Cache Management Support Routines for the i386
3 */
4
5#include <rtems.h>
6#include <rtems/score/cpu.h>
7#include <libcpu/page.h>
8
9#define I386_CACHE_ALIGNMENT 16
10#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
11#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
12
13void _CPU_disable_cache(void)
14{
15  unsigned int regCr0;
16
17  regCr0 = i386_get_cr0();
18  regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
19  regCr0 |= CR0_NO_WRITE_THROUGH;
20  i386_set_cr0( regCr0 );
21  rtems_cache_flush_entire_data();
22}
23
24/*
25 * Enable the entire cache
26 */
27
28void _CPU_enable_cache(void)
29{
30  unsigned int regCr0;
31
32  regCr0 = i386_get_cr0();
33  regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
34  regCr0 &= ~(CR0_NO_WRITE_THROUGH);
35  i386_set_cr0( regCr0 );
36  /*rtems_cache_flush_entire_data();*/
37}
38
39/*
40 * CACHE MANAGER: The following functions are CPU-specific.
41 * They provide the basic implementation for the rtems_* cache
42 * management routines. If a given function has no meaning for the CPU,
43 * it does nothing by default.
44 *
45 * FIXME: The routines below should be implemented per CPU,
46 *        to accomodate the capabilities of each.
47 */
48
49#if defined(I386_CACHE_ALIGNMENT)
50static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
51static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
52static void _CPU_cache_freeze_data(void) {}
53static void _CPU_cache_unfreeze_data(void) {}
54static void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
55static void _CPU_cache_freeze_instruction(void) {}
56static void _CPU_cache_unfreeze_instruction(void) {}
57
58static void _CPU_cache_flush_entire_data(void)
59{
60  __asm__ volatile ("wbinvd");
61}
62static void _CPU_cache_invalidate_entire_data(void)
63{
64  __asm__ volatile ("invd");
65}
66
67static void _CPU_cache_enable_data(void)
68{
69        _CPU_enable_cache();
70}
71
72static void _CPU_cache_disable_data(void)
73{
74        _CPU_disable_cache();
75}
76
77static void _CPU_cache_invalidate_entire_instruction(void)
78{
79  __asm__ volatile ("invd");
80}
81
82static void _CPU_cache_enable_instruction(void)
83{
84  _CPU_enable_cache();
85}
86
87static void _CPU_cache_disable_instruction( void )
88{
89  _CPU_disable_cache();
90}
91#endif
92
93#include "../../../shared/cache/cacheimpl.h"
Note: See TracBrowser for help on using the repository browser.