source: rtems/bsps/i386/shared/cache/cache.c

Last change on this file was 12dfe5dc, checked in by Joel Sherrill <joel@…>, on 01/16/19 at 21:42:18

bsps/i386/shared/cache/cache.c: Make compile

  • Property mode set to 100644
File size: 2.2 KB
RevLine 
[cf1f72e]1/*
2 *  Cache Management Support Routines for the i386
3 */
4
5#include <rtems.h>
[328bd35]6#include <rtems/score/cpu.h>
7#include <libcpu/page.h>
[cf1f72e]8
[4cf93658]9#define I386_CACHE_ALIGNMENT 16
10#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
[750e795]11#define CPU_INSTRUCTION_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
[4cf93658]12
[e6e63f8]13void _CPU_disable_cache(void)
14{
[665285f]15  unsigned int regCr0;
[cf1f72e]16
[665285f]17  regCr0 = i386_get_cr0();
18  regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
19  regCr0 |= CR0_NO_WRITE_THROUGH;
20  i386_set_cr0( regCr0 );
[5e77d129]21  rtems_cache_flush_entire_data();
[cf1f72e]22}
23
24/*
25 * Enable the entire cache
26 */
27
[e6e63f8]28void _CPU_enable_cache(void)
29{
[665285f]30  unsigned int regCr0;
[cf1f72e]31
[665285f]32  regCr0 = i386_get_cr0();
33  regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
34  regCr0 &= ~(CR0_NO_WRITE_THROUGH);
35  i386_set_cr0( regCr0 );
[5e77d129]36  /*rtems_cache_flush_entire_data();*/
[cf1f72e]37}
38
39/*
40 * CACHE MANAGER: The following functions are CPU-specific.
41 * They provide the basic implementation for the rtems_* cache
42 * management routines. If a given function has no meaning for the CPU,
43 * it does nothing by default.
44 *
[5e77d129]45 * FIXME: The routines below should be implemented per CPU,
[cf1f72e]46 *        to accomodate the capabilities of each.
47 */
48
49#if defined(I386_CACHE_ALIGNMENT)
[4cf93658]50static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
51static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
52static void _CPU_cache_freeze_data(void) {}
53static void _CPU_cache_unfreeze_data(void) {}
54static void _CPU_cache_flush_entire_data(void)
[cf1f72e]55{
[550c1b23]56  __asm__ volatile ("wbinvd");
[cf1f72e]57}
[12dfe5dc]58
[4cf93658]59static void _CPU_cache_invalidate_entire_data(void)
[cf1f72e]60{
[550c1b23]61  __asm__ volatile ("invd");
[cf1f72e]62}
63
[12dfe5dc]64static void _CPU_cache_invalidate_entire_instruction(void)
65{
66  __asm__ volatile ("invd");
67}
68
69static void _CPU_cache_invalidate_1_instruction_line(const void *i_addr)
70{
71  _CPU_cache_invalidate_entire_instruction();
72}
73
[4cf93658]74static void _CPU_cache_enable_data(void)
[cf1f72e]75{
76  _CPU_enable_cache();
77}
78
[bb6eeabf]79static void _CPU_cache_disable_data(void)
[cf1f72e]80{
81  _CPU_disable_cache();
82}
[bb6eeabf]83
[12dfe5dc]84static void _CPU_cache_enable_instruction(void)
85{
86  _CPU_enable_cache();
87}
88
89static void _CPU_cache_disable_instruction(void)
90{
91  _CPU_disable_cache();
92}
93
94static void _CPU_cache_freeze_instruction(void)
95{
96}
97
98static void _CPU_cache_unfreeze_instruction(void)
99{
100}
101
[cf1f72e]102#endif
[4cf93658]103
104#include "../../../shared/cache/cacheimpl.h"
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