source: rtems/bsps/i386/pc386/start/smp-imps.c @ 208cd6b

5
Last change on this file since 208cd6b was 208cd6b, checked in by Jan Sommer <jan.sommer@…>, on May 31, 2020 at 2:22:57 PM

bsps/pc386: Separate smp API functions. Makes smpfatal08 link

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1/*
2 * Author: Erich Boleyn  <erich@uruk.org>
3 *         http://www.uruk.org/~erich/
4 *
5 * Copyright (c) 1997-2011 Erich Boleyn.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 *  Source file implementing Intel MultiProcessor Specification (MPS)
32 *  version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
33 *  with hooks for running correctly on a standard PC without the hardware.
34 *
35 *  This file was created from information in the Intel MPS version 1.4
36 *  document, order number 242016-004, which can be ordered from the
37 *  Intel literature center.
38 *
39 *  General limitations of this code:
40 *
41 *   (1) : This code has never been tested on an MPS-compatible system with
42 *           486 CPUs, but is expected to work.
43 *   (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and
44 *       that 32-bit pointers and memory addressing is used uniformly.
45 */
46
47#define _SMP_IMPS_C
48
49/*
50 *  Includes here
51 */
52#if 0
53#define IMPS_DEBUG
54#endif
55
56#include <bsp/apic.h>
57#include <bsp/smp-imps.h>
58#include <bsp/irq.h>
59#include <rtems/score/smpimpl.h>
60
61/*
62 *  XXXXX  The following absolutely must be defined!!!
63 *
64 *  The "KERNEL_PRINT" could be made a null macro with no danger, of
65 *  course, but pretty much nothing would work without the other
66 *  ones defined.
67 */
68
69#if 0
70#define KERNEL_PRINT(x)       /* some kind of print function */
71#define CMOS_WRITE_BYTE(x,y)  /* write unsigned char "y" at CMOS loc "x" */
72#define CMOS_READ_BYTE(x)     /* read unsigned char at CMOS loc "x" */
73#define PHYS_TO_VIRTUAL(x)    /* convert physical address "x" to virtual */
74#define VIRTUAL_TO_PHYS(x)    /* convert virtual address "x" to physical */
75#define UDELAY(x)             /* delay roughly at least "x" microsecs */
76#define READ_MSR_LO(x)        /* Read MSR low function */
77#else
78#include <string.h>
79#include <unistd.h>
80#include <rtems.h>
81#include <rtems/bspIo.h>
82#include <rtems/score/cpu.h>
83#include <assert.h>
84
85extern void _pc386_delay(void);
86extern uint32_t* gdtdesc;
87
88static int lapic_dummy = 0;
89unsigned imps_lapic_addr = ((unsigned)(&lapic_dummy)) - LAPIC_ID;
90
91/* #define KERNEL_PRINT(_format)       printk(_format) */
92
93static void CMOS_WRITE_BYTE(
94  unsigned int  offset,
95  unsigned char value
96)
97{
98  if ( offset < 128 ) {
99    outport_byte( 0x70, offset );
100    outport_byte( 0x71, value );
101  } else {
102    outport_byte( 0x72, offset );
103    outport_byte( 0x73, value );
104  }
105}
106
107static unsigned char CMOS_READ_BYTE(
108  unsigned int  offset
109)
110{
111  unsigned char value;
112  if ( offset < 128 ) {
113    outport_byte( 0x70, offset );
114    inport_byte( 0x71, value );
115  } else {
116    outport_byte( 0x72, offset );
117    inport_byte( 0x73, value );
118  }
119  return value;
120}
121
122#define PHYS_TO_VIRTUAL(_x)    _x
123#define VIRTUAL_TO_PHYS(_x)    _x
124static void UDELAY(int x)
125{ int _i = x;
126  while ( _i-- )
127    _pc386_delay();
128}
129
130#define READ_MSR_LO(_x) \
131  (unsigned int)(read_msr(_x) & 0xffffffff)
132
133static inline unsigned long long read_msr(unsigned int msr)
134{
135  unsigned long long value;
136
137  asm volatile("rdmsr" : "=A" (value) : "c" (msr));
138  return value;
139}
140#endif
141
142/*
143 *  Defines that are here so as not to be in the global header file.
144 */
145#define EBDA_SEG_ADDR       0x40E
146#define BIOS_RESET_VECTOR   0x467
147#define LAPIC_ADDR_DEFAULT  0xFEE00000uL
148#define IOAPIC_ADDR_DEFAULT 0xFEC00000uL
149#define CMOS_RESET_CODE     0xF
150#define CMOS_RESET_JUMP     0xa
151#define CMOS_BASE_MEMORY    0x15
152
153/*
154 *  Static defines here for SMP use.
155 */
156
157#define DEF_ENTRIES  23
158
159static struct {
160  imps_processor proc[2];
161  imps_bus bus[2];
162  imps_ioapic ioapic;
163  imps_interrupt intin[16];
164  imps_interrupt lintin[2];
165} defconfig = {
166  { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0},
167    { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} },
168  { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}},
169    { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} },
170  { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT },
171  { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0},
172    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1},
173    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2},
174    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3},
175    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4},
176    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5},
177    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6},
178    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7},
179    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8},
180    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9},
181    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10},
182    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11},
183    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12},
184    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13},
185    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14},
186    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} },
187  { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0},
188    { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} }
189};
190
191/*
192 *  Exported globals here.
193 */
194
195volatile int imps_release_cpus = 0;
196int imps_enabled = 0;
197int imps_num_cpus = 1;
198unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
199unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
200
201/* now defined in getcpuid.c */
202extern unsigned imps_lapic_addr;
203
204static void secondary_cpu_initialize(void);
205
206/*
207 *  MPS checksum function
208 *
209 *  Function finished.
210 */
211static int
212get_checksum(unsigned start, int length)
213{
214  unsigned sum = 0;
215
216  while (length-- > 0) {
217    sum += *((unsigned char *) (start++));
218  }
219
220  return (sum&0xFF);
221}
222
223/*
224 *  APIC ICR write and status check function.
225 */
226int
227send_ipi(unsigned int dst, unsigned int v)
228{
229  int to, send_status;
230
231  IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24));
232  IMPS_LAPIC_WRITE(LAPIC_ICR, v);
233
234  /* Wait for send to finish */
235  to = 0;
236  do {
237    UDELAY(100);
238    send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND;
239  } while (send_status && (to++ < 1000));
240
241  return (to < 1000);
242}
243
244/*
245 *  Primary function for booting individual CPUs.
246 *
247 *  This must be modified to perform whatever OS-specific initialization
248 *  that is required.
249 */
250static int
251boot_cpu(imps_processor *proc)
252{
253  int apicid = proc->apic_id, success = 1;
254  unsigned bootaddr;
255  unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR);
256
257  /*
258   * Copy boot code for secondary CPUs here.  Find it in between
259   * "patch_code_start" and "patch_code_end" symbols.  The other CPUs
260   * will start there in 16-bit real mode under the 1MB boundary.
261   * "patch_code_start" should be placed at a 4K-aligned address
262   * under the 1MB boundary.
263   */
264
265  volatile uint32_t *reset;
266
267  bootaddr = (512-64)*1024;
268  reset= (volatile uint32_t *)bootaddr;
269
270  memcpy(
271    (char *) bootaddr,
272    _binary_appstart_bin_start,
273    (size_t)_binary_appstart_bin_size
274  );
275
276  /* Pass start function, stack region and gdtdescr to AP
277   * see startAP.S for location */
278  reset[1] = (uint32_t)secondary_cpu_initialize;
279  reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high;
280  memcpy(
281        (char*) &reset[3],
282        &gdtdesc,
283        6);
284  /*
285   *  Generic CPU startup sequence starts here.
286   */
287
288  /* set BIOS reset vector */
289  CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP);
290  *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12);
291
292  /* clear the APIC error register */
293  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
294  IMPS_LAPIC_READ(LAPIC_ESR);
295
296  /* assert INIT IPI */
297  send_ipi(
298    apicid,
299    LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT
300  );
301  UDELAY(10000);
302
303  /* de-assert INIT IPI */
304  send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
305
306  UDELAY(10000);
307
308  /*
309   *  Send Startup IPIs if not an old pre-integrated APIC.
310   */
311
312  if (proc->apic_ver >= APIC_VER_NEW) {
313    int i;
314    for (i = 1; i <= 2; i++) {
315      send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
316      UDELAY(1000);
317    }
318  }
319
320  /*
321   *  Wait until AP is in protected mode before starting the next AP
322   */
323  while (reset[2] != 0);
324
325  /*
326   *  Generic CPU startup sequence ends here, the rest is cleanup.
327   */
328
329  /* clear the APIC error register */
330  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
331  IMPS_LAPIC_READ(LAPIC_ESR);
332
333  /* clean up BIOS reset vector */
334  CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
335  *((volatile unsigned *) bios_reset_vector) = 0;
336
337  return success;
338}
339
340/*
341 *  read bios stuff and fill tables
342 */
343static void
344add_processor(imps_processor *proc)
345{
346  int apicid = proc->apic_id;
347
348  printk("  Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver);
349  if (!(proc->flags & IMPS_FLAG_ENABLED)) {
350    printk("DISABLED\n");
351    return;
352  }
353  if (proc->flags & (IMPS_CPUFLAG_BOOT)) {
354    printk("#0  BootStrap Processor (BSP)\n");
355    return;
356  }
357  /* Setup the apic/cpu maps before booting the APs
358   * otherwise calls to _Get_current_processor can deliver
359   * wrong values if the BSP gets interrupted
360   */
361  imps_cpu_apic_map[imps_num_cpus] = apicid;
362  imps_apic_cpu_map[apicid] = imps_num_cpus;
363  if (boot_cpu(proc)) {
364
365    /*  XXXXX  add OS-specific setup for secondary CPUs here */
366
367    /* AP booted successfully, increase number of available cores */
368    imps_num_cpus++;
369    printk("#%d  Application Processor (AP)\n", imps_apic_cpu_map[apicid]);
370  }
371}
372
373
374static void
375add_bus(imps_bus *bus)
376{
377  char str[8];
378
379  memcpy(str, bus->bus_type, 6);
380  str[6] = 0;
381  printk("  Bus id %d is %s\n", bus->id, str);
382
383  /*  XXXXX  add OS-specific code here */
384}
385
386static void
387add_ioapic(imps_ioapic *ioapic)
388{
389  printk("  I/O APIC id %d ver %d, address: 0x%x  ",
390          ioapic->id, ioapic->ver, ioapic->addr);
391  if (!(ioapic->flags & IMPS_FLAG_ENABLED)) {
392    printk("DISABLED\n");
393    return;
394  }
395  printk("\n");
396
397  /*  XXXXX  add OS-specific code here */
398}
399
400static void
401imps_read_config_table(unsigned start, int count)
402{
403  while (count-- > 0) {
404    switch (*((unsigned char *)start)) {
405    case IMPS_BCT_PROCESSOR:
406      if ( imps_num_cpus < rtems_configuration_get_maximum_processors() ) {
407        if (_SMP_Should_start_processor((uint32_t) imps_num_cpus)) {
408          add_processor((imps_processor *)start);
409        }
410      } else
411        imps_num_cpus++;
412      start += 12;  /* 20 total */
413      break;
414    case IMPS_BCT_BUS:
415      add_bus((imps_bus *)start);
416      break;
417    case IMPS_BCT_IOAPIC:
418      add_ioapic((imps_ioapic *)start);
419      break;
420#if 0  /*  XXXXX  uncomment this if "add_io_interrupt" is implemented */
421    case IMPS_BCT_IO_INTERRUPT:
422      add_io_interrupt((imps_interrupt *)start);
423      break;
424#endif
425#if 0  /*  XXXXX  uncomment this if "add_local_interrupt" is implemented */
426    case IMPS_BCT_LOCAL_INTERRUPT:
427      add_local_interupt((imps_interrupt *)start);
428      break;
429#endif
430    default:
431      break;
432    }
433    start += 8;
434  }
435  if ( imps_num_cpus > rtems_configuration_get_maximum_processors() ) {
436    printk(
437      "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n",
438      imps_num_cpus - 1,
439      rtems_configuration_get_maximum_processors()
440    );
441    imps_num_cpus = rtems_configuration_get_maximum_processors();
442    return;
443  }
444}
445
446static int
447imps_bad_bios(imps_fps *fps_ptr)
448{
449  int sum;
450  imps_cth *local_cth_ptr
451    = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
452
453  if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) {
454    printk("    Invalid MP System Configuration type %d\n",
455            fps_ptr->feature_info[0]);
456    return 1;
457  }
458
459  if (fps_ptr->cth_ptr) {
460    sum = get_checksum((unsigned)local_cth_ptr,
461                                   local_cth_ptr->base_length);
462    if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) {
463      printk(
464        "    Bad MP Config Table sig 0x%x and/or checksum 0x%x\n",
465        (unsigned)(fps_ptr->cth_ptr),
466        sum
467      );
468      return 1;
469    }
470    if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) {
471      printk(
472        "    Bad MP Config Table sub-revision # %d\n",
473        local_cth_ptr->spec_rev
474      );
475      return 1;
476    }
477    if (local_cth_ptr->extended_length) {
478      sum = (get_checksum(((unsigned)local_cth_ptr)
479              + local_cth_ptr->base_length,
480              local_cth_ptr->extended_length)
481             + local_cth_ptr->extended_checksum) & 0xFF;
482      if (sum) {
483        printk("    Bad Extended MP Config Table checksum 0x%x\n", sum);
484        return 1;
485      }
486    }
487  } else if (!fps_ptr->feature_info[0]) {
488    printk("    Missing configuration information\n");
489    return 1;
490  }
491
492  return 0;
493}
494
495static void
496imps_read_bios(imps_fps *fps_ptr)
497{
498  int apicid;
499  unsigned cth_start, cth_count;
500  imps_cth *local_cth_ptr
501    = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
502  char *str_ptr;
503
504  printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n",
505          fps_ptr->spec_rev);
506
507  /*
508   *  Do all checking of errors which would definitely
509   *  lead to failure of the SMP boot here.
510   */
511  if (imps_bad_bios(fps_ptr)) {
512    printk("    Disabling MPS support\n");
513    return;
514  }
515
516  if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) {
517    str_ptr = "IMCR and PIC";
518  } else {
519    str_ptr = "Virtual Wire";
520  }
521  if (fps_ptr->cth_ptr) {
522    imps_lapic_addr = local_cth_ptr->lapic_addr;
523  } else {
524    imps_lapic_addr = LAPIC_ADDR_DEFAULT;
525  }
526  printk("    APIC config: \"%s mode\"    Local APIC address: 0x%x\n",
527          str_ptr, imps_lapic_addr);
528  if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) {
529    printk("Inconsistent Local APIC address, Disabling SMP support\n");
530    return;
531  }
532  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
533
534  /*
535   *  Setup primary CPU.
536   */
537  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
538  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
539  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
540  imps_cpu_apic_map[0] = apicid;
541  imps_apic_cpu_map[apicid] = 0;
542
543  if (fps_ptr->cth_ptr) {
544    char str1[16], str2[16];
545    memcpy(str1, local_cth_ptr->oem_id, 8);
546    str1[8] = 0;
547    memcpy(str2, local_cth_ptr->prod_id, 12);
548    str2[12] = 0;
549    printk("  OEM id: %s  Product id: %s\n", str1, str2);
550    cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth);
551    cth_count = local_cth_ptr->entry_count;
552  } else {
553    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_ID;
554    defconfig.ioapic.id
555      = APIC_ID(*((volatile unsigned *)
556            (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
557    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_VER;
558    defconfig.ioapic.ver
559      = APIC_VERSION(*((volatile unsigned *)
560           (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
561    defconfig.proc[apicid].flags
562      = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT;
563    defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED;
564    imps_num_cpus = 2;
565    if (fps_ptr->feature_info[0] == 1
566     || fps_ptr->feature_info[0] == 5) {
567      memcpy(defconfig.bus[0].bus_type, "ISA   ", 6);
568    }
569    if (fps_ptr->feature_info[0] == 4
570     || fps_ptr->feature_info[0] == 7) {
571      memcpy(defconfig.bus[0].bus_type, "MCA   ", 6);
572    }
573    if (fps_ptr->feature_info[0] > 4) {
574      defconfig.proc[0].apic_ver = 0x10;
575      defconfig.proc[1].apic_ver = 0x10;
576      defconfig.bus[1].type = IMPS_BCT_BUS;
577    }
578    if (fps_ptr->feature_info[0] == 2) {
579      defconfig.intin[2].type = 255;
580      defconfig.intin[13].type = 255;
581    }
582    if (fps_ptr->feature_info[0] == 7) {
583      defconfig.intin[0].type = 255;
584    }
585    cth_start = (unsigned) &defconfig;
586    cth_count = DEF_ENTRIES;
587  }
588  imps_read_config_table(cth_start, cth_count);
589
590  /* %%%%% ESB read extended entries here */
591
592  imps_enabled = 1;
593}
594
595/*
596 *  Given a region to check, this actually looks for the "MP Floating
597 *  Pointer Structure".  The return value indicates if the correct
598 *  signature and checksum for a floating pointer structure of the
599 *  appropriate spec revision was found.  If so, then do not search
600 *  further.
601 *
602 *  NOTE:  The memory scan will always be in the bottom 1 MB.
603 *
604 *  This function presumes that "start" will always be aligned to a 16-bit
605 *  boundary.
606 *
607 *  Function finished.
608 */
609static int
610imps_scan(unsigned start, unsigned length)
611{
612  printk("Scanning from 0x%x for %d bytes\n", start, length);
613
614  while (length > 0) {
615    imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start);
616
617    if (fps_ptr->sig == IMPS_FPS_SIGNATURE
618     && fps_ptr->length == 1
619     && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4)
620     && !get_checksum(start, 16)) {
621      printk("Found MP Floating Structure Pointer at %x\n", start);
622      imps_read_bios(fps_ptr);
623      return 1;
624    }
625
626    length -= 16;
627    start += 16;
628  }
629
630  return 0;
631}
632
633#if !defined(__rtems__)
634/*
635 *  This is the primary function to "force" SMP support, with
636 *  the assumption that you have consecutively numbered APIC ids.
637 */
638int
639imps_force(int ncpus)
640{
641  int apicid, i;
642  imps_processor p;
643
644  printk("Intel MultiProcessor \"Force\" Support\n");
645
646  imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000);
647  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
648
649  /*
650   *  Setup primary CPU.
651   */
652  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
653  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
654  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
655  imps_cpu_apic_map[0] = apicid;
656  imps_apic_cpu_map[apicid] = 0;
657
658  p.type = 0;
659  p.apic_ver = 0x10;
660  p.signature = p.features = 0;
661
662  for (i = 0; i < ncpus; i++) {
663    if (apicid == i) {
664      p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT;
665    } else {
666      p.flags = IMPS_FLAG_ENABLED;
667    }
668    p.apic_id = i;
669    add_processor(&p);
670  }
671
672  return imps_num_cpus;
673}
674#endif
675
676/*
677 *  This is the primary function for probing for MPS compatible hardware
678 *  and BIOS information.  Call this during the early stages of OS startup,
679 *  before memory can be messed up.
680 *
681 *  The probe looks for the "MP Floating Pointer Structure" at locations
682 *  listed at the top of page 4-2 of the spec.
683 *
684 *  Environment requirements from the OS to run:
685 *
686 *   (1) : A non-linear virtual to physical memory mapping is probably OK,
687 *       as (I think) the structures all fall within page boundaries,
688 *       but a linear mapping is recommended.  Currently assumes that
689 *       the mapping will remain identical over time (which should be
690 *       OK since it only accesses memory which shouldn't be munged
691 *       by the OS anyway).
692 *   (2) : The OS only consumes memory which the BIOS says is OK to use,
693 *       and not any of the BIOS standard areas (the areas 0x400 to
694 *       0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical
695 *       RAM).  Sometimes a small amount of physical RAM is not
696 *       reported by the BIOS, to be used to store MPS and other
697 *       information.
698 *   (3) : It must be possible to read the CMOS.
699 *   (4) : There must be between 512K and 640K of lower memory (this is a
700 *       sanity check).
701 *
702 *  Function finished.
703 */
704int
705imps_probe(void)
706{
707  /*
708   *  Determine possible address of the EBDA
709   */
710  unsigned ebda_addr = *((unsigned short *)
711             PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4;
712
713  /*
714   *  Determine amount of installed lower memory (not *available*
715   *  lower memory).
716   *
717   *  NOTE:  This should work reliably as long as we verify the
718   *         machine is at least a system that could possibly have
719   *         MPS compatibility to begin with.
720   */
721  unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8)
722            | CMOS_READ_BYTE(CMOS_BASE_MEMORY))       << 10;
723
724#ifdef IMPS_DEBUG
725  imps_enabled = 0;
726  imps_num_cpus = 1;
727#endif
728
729  /*
730   *  Sanity check : if this isn't reasonable, it is almost impossibly
731   *    unlikely to be an MPS compatible machine, so return failure.
732   */
733  if (mem_lower < 512*1024 || mem_lower > 640*1024) {
734    return 0;
735  }
736
737  if (ebda_addr > mem_lower - 1024
738   || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr))
739         * 1024 > mem_lower) {
740    ebda_addr = 0;
741  }
742
743  if (((ebda_addr && imps_scan(ebda_addr, 1024))
744   || (!ebda_addr && imps_scan(mem_lower - 1024, 1024))
745   || imps_scan(0xF0000, 0x10000)) && imps_enabled) {
746    return imps_num_cpus;
747  }
748
749  /*
750   *  If no BIOS info on MPS hardware is found, then return failure.
751   */
752
753  return 0;
754}
755
756/*
757 *  RTEMS SMP BSP Support
758 */
759static void smp_apic_ack(void)
760{
761  (void) IMPS_LAPIC_READ(LAPIC_SPIV);  /* dummy read */
762  IMPS_LAPIC_WRITE(LAPIC_EOI, 0 );     /* ACK the interrupt */
763}
764
765static void bsp_inter_processor_interrupt(void *arg)
766{
767  (void) arg;
768
769  smp_apic_ack();
770
771  _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
772}
773
774void
775ipi_install_irq(void)
776{
777  rtems_status_code status;
778
779  status = rtems_interrupt_handler_install(
780    16,
781    "smp-imps",
782    RTEMS_INTERRUPT_UNIQUE,
783    bsp_inter_processor_interrupt,
784    NULL
785  );
786  assert(status == RTEMS_SUCCESSFUL);
787}
788
789#ifdef __SSE__
790extern void enable_sse(void);
791#endif
792
793/* pc386 specific initialization */
794static void secondary_cpu_initialize(void)
795{
796  int apicid;
797
798  asm volatile( "lidt IDT_Descriptor" );
799
800  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
801  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
802
803#ifdef __SSE__
804  enable_sse();
805#endif
806
807  _SMP_Start_multitasking_on_secondary_processor( _Per_CPU_Get() );
808}
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