[1d007c60] | 1 | /* |
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[47bae47] | 2 | * Author: Erich Boleyn <erich@uruk.org> |
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| 3 | * http://www.uruk.org/~erich/ |
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[1d007c60] | 4 | * |
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[47bae47] | 5 | * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. |
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[1d007c60] | 6 | * |
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[47bae47] | 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions |
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| 9 | * are met: |
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| 10 | * 1. Redistributions of source code must retain the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer. |
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in the |
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| 14 | * documentation and/or other materials provided with the distribution. |
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| 15 | * 3. The name of the author may not be used to endorse or promote products |
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| 16 | * derived from this software without specific prior written permission. |
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| 17 | * |
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 28 | */ |
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| 29 | |
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| 30 | /* |
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[1d007c60] | 31 | * Source file implementing Intel MultiProcessor Specification (MPS) |
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| 32 | * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, |
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| 33 | * with hooks for running correctly on a standard PC without the hardware. |
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| 34 | * |
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| 35 | * This file was created from information in the Intel MPS version 1.4 |
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| 36 | * document, order number 242016-004, which can be ordered from the |
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| 37 | * Intel literature center. |
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| 38 | * |
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| 39 | * General limitations of this code: |
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| 40 | * |
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| 41 | * (1) : This code has never been tested on an MPS-compatible system with |
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| 42 | * 486 CPUs, but is expected to work. |
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| 43 | * (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and |
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[894a2c91] | 44 | * that 32-bit pointers and memory addressing is used uniformly. |
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[1d007c60] | 45 | */ |
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| 46 | |
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| 47 | #define _SMP_IMPS_C |
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| 48 | |
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[01f2692e] | 49 | /* |
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| 50 | * Includes here |
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| 51 | */ |
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| 52 | #if 0 |
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| 53 | #define IMPS_DEBUG |
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| 54 | #endif |
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| 55 | |
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| 56 | #include <bsp/apic.h> |
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| 57 | #include <bsp/smp-imps.h> |
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[b23abb48] | 58 | #include <bsp/irq.h> |
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[911b1d2] | 59 | #include <rtems/score/smpimpl.h> |
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[01f2692e] | 60 | |
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[1d007c60] | 61 | /* |
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| 62 | * XXXXX The following absolutely must be defined!!! |
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| 63 | * |
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| 64 | * The "KERNEL_PRINT" could be made a null macro with no danger, of |
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| 65 | * course, but pretty much nothing would work without the other |
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| 66 | * ones defined. |
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| 67 | */ |
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| 68 | |
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| 69 | #if 0 |
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[894a2c91] | 70 | #define KERNEL_PRINT(x) /* some kind of print function */ |
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| 71 | #define CMOS_WRITE_BYTE(x,y) /* write unsigned char "y" at CMOS loc "x" */ |
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| 72 | #define CMOS_READ_BYTE(x) /* read unsigned char at CMOS loc "x" */ |
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| 73 | #define PHYS_TO_VIRTUAL(x) /* convert physical address "x" to virtual */ |
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| 74 | #define VIRTUAL_TO_PHYS(x) /* convert virtual address "x" to physical */ |
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| 75 | #define UDELAY(x) /* delay roughly at least "x" microsecs */ |
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| 76 | #define READ_MSR_LO(x) /* Read MSR low function */ |
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[01f2692e] | 77 | #else |
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| 78 | #include <string.h> |
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| 79 | #include <unistd.h> |
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| 80 | #include <rtems.h> |
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| 81 | #include <rtems/bspIo.h> |
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[328bd35] | 82 | #include <rtems/score/cpu.h> |
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[2bdcf4fd] | 83 | #include <assert.h> |
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[01f2692e] | 84 | |
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| 85 | extern void _pc386_delay(void); |
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[85d6a760] | 86 | extern uint32_t* gdtdesc; |
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[01f2692e] | 87 | |
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[208cd6b] | 88 | static int lapic_dummy = 0; |
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| 89 | unsigned imps_lapic_addr = ((unsigned)(&lapic_dummy)) - LAPIC_ID; |
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| 90 | |
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[01f2692e] | 91 | /* #define KERNEL_PRINT(_format) printk(_format) */ |
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| 92 | |
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| 93 | static void CMOS_WRITE_BYTE( |
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| 94 | unsigned int offset, |
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| 95 | unsigned char value |
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| 96 | ) |
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| 97 | { |
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| 98 | if ( offset < 128 ) { |
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| 99 | outport_byte( 0x70, offset ); |
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| 100 | outport_byte( 0x71, value ); |
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| 101 | } else { |
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| 102 | outport_byte( 0x72, offset ); |
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| 103 | outport_byte( 0x73, value ); |
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| 104 | } |
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| 105 | } |
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[1d007c60] | 106 | |
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[01f2692e] | 107 | static unsigned char CMOS_READ_BYTE( |
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| 108 | unsigned int offset |
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| 109 | ) |
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| 110 | { |
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| 111 | unsigned char value; |
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| 112 | if ( offset < 128 ) { |
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| 113 | outport_byte( 0x70, offset ); |
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| 114 | inport_byte( 0x71, value ); |
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| 115 | } else { |
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| 116 | outport_byte( 0x72, offset ); |
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| 117 | inport_byte( 0x73, value ); |
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| 118 | } |
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| 119 | return value; |
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| 120 | } |
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[1d007c60] | 121 | |
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[01f2692e] | 122 | #define PHYS_TO_VIRTUAL(_x) _x |
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| 123 | #define VIRTUAL_TO_PHYS(_x) _x |
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| 124 | static void UDELAY(int x) |
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| 125 | { int _i = x; |
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| 126 | while ( _i-- ) |
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| 127 | _pc386_delay(); |
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| 128 | } |
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[2bdcf4fd] | 129 | |
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[01f2692e] | 130 | #define READ_MSR_LO(_x) \ |
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| 131 | (unsigned int)(read_msr(_x) & 0xffffffff) |
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[1d007c60] | 132 | |
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[01f2692e] | 133 | static inline unsigned long long read_msr(unsigned int msr) |
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| 134 | { |
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| 135 | unsigned long long value; |
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[2bdcf4fd] | 136 | |
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[01f2692e] | 137 | asm volatile("rdmsr" : "=A" (value) : "c" (msr)); |
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| 138 | return value; |
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| 139 | } |
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| 140 | #endif |
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[1d007c60] | 141 | |
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| 142 | /* |
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| 143 | * Defines that are here so as not to be in the global header file. |
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| 144 | */ |
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[894a2c91] | 145 | #define EBDA_SEG_ADDR 0x40E |
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| 146 | #define BIOS_RESET_VECTOR 0x467 |
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| 147 | #define LAPIC_ADDR_DEFAULT 0xFEE00000uL |
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| 148 | #define IOAPIC_ADDR_DEFAULT 0xFEC00000uL |
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| 149 | #define CMOS_RESET_CODE 0xF |
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| 150 | #define CMOS_RESET_JUMP 0xa |
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| 151 | #define CMOS_BASE_MEMORY 0x15 |
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[1d007c60] | 152 | |
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| 153 | /* |
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| 154 | * Static defines here for SMP use. |
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| 155 | */ |
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| 156 | |
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[894a2c91] | 157 | #define DEF_ENTRIES 23 |
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[1d007c60] | 158 | |
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| 159 | static struct { |
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[894a2c91] | 160 | imps_processor proc[2]; |
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| 161 | imps_bus bus[2]; |
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| 162 | imps_ioapic ioapic; |
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| 163 | imps_interrupt intin[16]; |
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| 164 | imps_interrupt lintin[2]; |
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[1d007c60] | 165 | } defconfig = { |
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[894a2c91] | 166 | { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0}, |
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| 167 | { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} }, |
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| 168 | { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}}, |
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| 169 | { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} }, |
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| 170 | { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT }, |
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| 171 | { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0}, |
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| 172 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1}, |
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| 173 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2}, |
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| 174 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3}, |
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| 175 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4}, |
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| 176 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5}, |
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| 177 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6}, |
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| 178 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7}, |
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| 179 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8}, |
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| 180 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9}, |
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| 181 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10}, |
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| 182 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11}, |
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| 183 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12}, |
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| 184 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13}, |
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| 185 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14}, |
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| 186 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} }, |
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| 187 | { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0}, |
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| 188 | { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} } |
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[1d007c60] | 189 | }; |
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| 190 | |
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| 191 | /* |
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| 192 | * Exported globals here. |
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| 193 | */ |
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| 194 | |
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| 195 | volatile int imps_release_cpus = 0; |
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| 196 | int imps_enabled = 0; |
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| 197 | int imps_num_cpus = 1; |
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| 198 | unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS]; |
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| 199 | unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS]; |
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| 200 | |
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[01f2692e] | 201 | /* now defined in getcpuid.c */ |
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| 202 | extern unsigned imps_lapic_addr; |
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| 203 | |
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[8cacceb] | 204 | static void secondary_cpu_initialize(void); |
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| 205 | |
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[1d007c60] | 206 | /* |
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| 207 | * MPS checksum function |
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| 208 | * |
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| 209 | * Function finished. |
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| 210 | */ |
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| 211 | static int |
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| 212 | get_checksum(unsigned start, int length) |
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| 213 | { |
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[894a2c91] | 214 | unsigned sum = 0; |
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[1d007c60] | 215 | |
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[894a2c91] | 216 | while (length-- > 0) { |
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| 217 | sum += *((unsigned char *) (start++)); |
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| 218 | } |
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[1d007c60] | 219 | |
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[894a2c91] | 220 | return (sum&0xFF); |
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[1d007c60] | 221 | } |
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| 222 | |
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| 223 | /* |
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| 224 | * APIC ICR write and status check function. |
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| 225 | */ |
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[208cd6b] | 226 | int |
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[1d007c60] | 227 | send_ipi(unsigned int dst, unsigned int v) |
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| 228 | { |
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[894a2c91] | 229 | int to, send_status; |
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[1d007c60] | 230 | |
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[894a2c91] | 231 | IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24)); |
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| 232 | IMPS_LAPIC_WRITE(LAPIC_ICR, v); |
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[1d007c60] | 233 | |
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[894a2c91] | 234 | /* Wait for send to finish */ |
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| 235 | to = 0; |
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| 236 | do { |
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| 237 | UDELAY(100); |
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| 238 | send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND; |
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| 239 | } while (send_status && (to++ < 1000)); |
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[1d007c60] | 240 | |
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[894a2c91] | 241 | return (to < 1000); |
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[1d007c60] | 242 | } |
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| 243 | |
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| 244 | /* |
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| 245 | * Primary function for booting individual CPUs. |
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| 246 | * |
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| 247 | * This must be modified to perform whatever OS-specific initialization |
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| 248 | * that is required. |
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| 249 | */ |
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[b23abb48] | 250 | static int |
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[1d007c60] | 251 | boot_cpu(imps_processor *proc) |
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| 252 | { |
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[01f2692e] | 253 | int apicid = proc->apic_id, success = 1; |
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[b23abb48] | 254 | unsigned bootaddr; |
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[894a2c91] | 255 | unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR); |
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| 256 | |
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| 257 | /* |
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| 258 | * Copy boot code for secondary CPUs here. Find it in between |
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| 259 | * "patch_code_start" and "patch_code_end" symbols. The other CPUs |
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| 260 | * will start there in 16-bit real mode under the 1MB boundary. |
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| 261 | * "patch_code_start" should be placed at a 4K-aligned address |
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| 262 | * under the 1MB boundary. |
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| 263 | */ |
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| 264 | |
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[85d6a760] | 265 | volatile uint32_t *reset; |
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[01f2692e] | 266 | |
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[894a2c91] | 267 | bootaddr = (512-64)*1024; |
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[85d6a760] | 268 | reset= (volatile uint32_t *)bootaddr; |
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[01f2692e] | 269 | |
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| 270 | memcpy( |
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| 271 | (char *) bootaddr, |
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| 272 | _binary_appstart_bin_start, |
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| 273 | (size_t)_binary_appstart_bin_size |
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| 274 | ); |
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| 275 | |
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[85d6a760] | 276 | /* Pass start function, stack region and gdtdescr to AP |
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| 277 | * see startAP.S for location */ |
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[8cacceb] | 278 | reset[1] = (uint32_t)secondary_cpu_initialize; |
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[fe52e7c0] | 279 | reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high; |
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[85d6a760] | 280 | memcpy( |
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| 281 | (char*) &reset[3], |
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| 282 | &gdtdesc, |
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| 283 | 6); |
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[894a2c91] | 284 | /* |
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| 285 | * Generic CPU startup sequence starts here. |
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| 286 | */ |
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| 287 | |
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| 288 | /* set BIOS reset vector */ |
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| 289 | CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP); |
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| 290 | *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12); |
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| 291 | |
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| 292 | /* clear the APIC error register */ |
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| 293 | IMPS_LAPIC_WRITE(LAPIC_ESR, 0); |
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[b23abb48] | 294 | IMPS_LAPIC_READ(LAPIC_ESR); |
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[894a2c91] | 295 | |
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| 296 | /* assert INIT IPI */ |
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| 297 | send_ipi( |
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[01f2692e] | 298 | apicid, |
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| 299 | LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT |
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| 300 | ); |
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[894a2c91] | 301 | UDELAY(10000); |
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| 302 | |
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| 303 | /* de-assert INIT IPI */ |
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| 304 | send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); |
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| 305 | |
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| 306 | UDELAY(10000); |
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| 307 | |
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| 308 | /* |
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| 309 | * Send Startup IPIs if not an old pre-integrated APIC. |
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| 310 | */ |
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| 311 | |
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| 312 | if (proc->apic_ver >= APIC_VER_NEW) { |
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| 313 | int i; |
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| 314 | for (i = 1; i <= 2; i++) { |
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| 315 | send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); |
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| 316 | UDELAY(1000); |
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| 317 | } |
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| 318 | } |
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| 319 | |
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[f99b1f0] | 320 | /* |
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| 321 | * Wait until AP is in protected mode before starting the next AP |
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| 322 | */ |
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| 323 | while (reset[2] != 0); |
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| 324 | |
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[894a2c91] | 325 | /* |
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| 326 | * Generic CPU startup sequence ends here, the rest is cleanup. |
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| 327 | */ |
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| 328 | |
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| 329 | /* clear the APIC error register */ |
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| 330 | IMPS_LAPIC_WRITE(LAPIC_ESR, 0); |
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[b23abb48] | 331 | IMPS_LAPIC_READ(LAPIC_ESR); |
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[894a2c91] | 332 | |
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| 333 | /* clean up BIOS reset vector */ |
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| 334 | CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0); |
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| 335 | *((volatile unsigned *) bios_reset_vector) = 0; |
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| 336 | |
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| 337 | return success; |
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[1d007c60] | 338 | } |
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| 339 | |
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| 340 | /* |
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| 341 | * read bios stuff and fill tables |
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| 342 | */ |
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| 343 | static void |
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| 344 | add_processor(imps_processor *proc) |
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| 345 | { |
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[894a2c91] | 346 | int apicid = proc->apic_id; |
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| 347 | |
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[01f2692e] | 348 | printk(" Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver); |
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[894a2c91] | 349 | if (!(proc->flags & IMPS_FLAG_ENABLED)) { |
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[01f2692e] | 350 | printk("DISABLED\n"); |
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[894a2c91] | 351 | return; |
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| 352 | } |
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| 353 | if (proc->flags & (IMPS_CPUFLAG_BOOT)) { |
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[01f2692e] | 354 | printk("#0 BootStrap Processor (BSP)\n"); |
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[894a2c91] | 355 | return; |
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| 356 | } |
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[f99b1f0] | 357 | /* Setup the apic/cpu maps before booting the APs |
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| 358 | * otherwise calls to _Get_current_processor can deliver |
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| 359 | * wrong values if the BSP gets interrupted |
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| 360 | */ |
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| 361 | imps_cpu_apic_map[imps_num_cpus] = apicid; |
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| 362 | imps_apic_cpu_map[apicid] = imps_num_cpus; |
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[894a2c91] | 363 | if (boot_cpu(proc)) { |
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| 364 | |
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| 365 | /* XXXXX add OS-specific setup for secondary CPUs here */ |
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| 366 | |
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[f99b1f0] | 367 | /* AP booted successfully, increase number of available cores */ |
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[894a2c91] | 368 | imps_num_cpus++; |
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[85d6a760] | 369 | printk("#%d Application Processor (AP)\n", imps_apic_cpu_map[apicid]); |
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[894a2c91] | 370 | } |
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[1d007c60] | 371 | } |
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| 372 | |
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| 373 | |
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| 374 | static void |
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| 375 | add_bus(imps_bus *bus) |
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| 376 | { |
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[894a2c91] | 377 | char str[8]; |
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[1d007c60] | 378 | |
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[894a2c91] | 379 | memcpy(str, bus->bus_type, 6); |
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| 380 | str[6] = 0; |
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[01f2692e] | 381 | printk(" Bus id %d is %s\n", bus->id, str); |
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[1d007c60] | 382 | |
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[894a2c91] | 383 | /* XXXXX add OS-specific code here */ |
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[1d007c60] | 384 | } |
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| 385 | |
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| 386 | static void |
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| 387 | add_ioapic(imps_ioapic *ioapic) |
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| 388 | { |
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[01f2692e] | 389 | printk(" I/O APIC id %d ver %d, address: 0x%x ", |
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| 390 | ioapic->id, ioapic->ver, ioapic->addr); |
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[894a2c91] | 391 | if (!(ioapic->flags & IMPS_FLAG_ENABLED)) { |
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[01f2692e] | 392 | printk("DISABLED\n"); |
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[894a2c91] | 393 | return; |
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| 394 | } |
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[01f2692e] | 395 | printk("\n"); |
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[894a2c91] | 396 | |
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| 397 | /* XXXXX add OS-specific code here */ |
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[1d007c60] | 398 | } |
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| 399 | |
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| 400 | static void |
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| 401 | imps_read_config_table(unsigned start, int count) |
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| 402 | { |
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[894a2c91] | 403 | while (count-- > 0) { |
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| 404 | switch (*((unsigned char *)start)) { |
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| 405 | case IMPS_BCT_PROCESSOR: |
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[6c2eedc] | 406 | if ( imps_num_cpus < rtems_configuration_get_maximum_processors() ) { |
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[2a4f9d7] | 407 | if (_SMP_Should_start_processor((uint32_t) imps_num_cpus)) { |
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[c5831a3f] | 408 | add_processor((imps_processor *)start); |
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| 409 | } |
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[2bdcf4fd] | 410 | } else |
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[01f2692e] | 411 | imps_num_cpus++; |
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[894a2c91] | 412 | start += 12; /* 20 total */ |
---|
| 413 | break; |
---|
| 414 | case IMPS_BCT_BUS: |
---|
| 415 | add_bus((imps_bus *)start); |
---|
| 416 | break; |
---|
| 417 | case IMPS_BCT_IOAPIC: |
---|
| 418 | add_ioapic((imps_ioapic *)start); |
---|
| 419 | break; |
---|
| 420 | #if 0 /* XXXXX uncomment this if "add_io_interrupt" is implemented */ |
---|
| 421 | case IMPS_BCT_IO_INTERRUPT: |
---|
| 422 | add_io_interrupt((imps_interrupt *)start); |
---|
| 423 | break; |
---|
[1d007c60] | 424 | #endif |
---|
[894a2c91] | 425 | #if 0 /* XXXXX uncomment this if "add_local_interrupt" is implemented */ |
---|
| 426 | case IMPS_BCT_LOCAL_INTERRUPT: |
---|
| 427 | add_local_interupt((imps_interrupt *)start); |
---|
| 428 | break; |
---|
[1d007c60] | 429 | #endif |
---|
[894a2c91] | 430 | default: |
---|
| 431 | break; |
---|
| 432 | } |
---|
| 433 | start += 8; |
---|
| 434 | } |
---|
[6c2eedc] | 435 | if ( imps_num_cpus > rtems_configuration_get_maximum_processors() ) { |
---|
[01f2692e] | 436 | printk( |
---|
| 437 | "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n", |
---|
| 438 | imps_num_cpus - 1, |
---|
[6c2eedc] | 439 | rtems_configuration_get_maximum_processors() |
---|
[01f2692e] | 440 | ); |
---|
[6c2eedc] | 441 | imps_num_cpus = rtems_configuration_get_maximum_processors(); |
---|
[01f2692e] | 442 | return; |
---|
| 443 | } |
---|
[1d007c60] | 444 | } |
---|
| 445 | |
---|
| 446 | static int |
---|
| 447 | imps_bad_bios(imps_fps *fps_ptr) |
---|
| 448 | { |
---|
[894a2c91] | 449 | int sum; |
---|
| 450 | imps_cth *local_cth_ptr |
---|
| 451 | = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr); |
---|
| 452 | |
---|
| 453 | if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) { |
---|
[01f2692e] | 454 | printk(" Invalid MP System Configuration type %d\n", |
---|
| 455 | fps_ptr->feature_info[0]); |
---|
[894a2c91] | 456 | return 1; |
---|
| 457 | } |
---|
| 458 | |
---|
| 459 | if (fps_ptr->cth_ptr) { |
---|
| 460 | sum = get_checksum((unsigned)local_cth_ptr, |
---|
[1d007c60] | 461 | local_cth_ptr->base_length); |
---|
[894a2c91] | 462 | if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) { |
---|
[01f2692e] | 463 | printk( |
---|
| 464 | " Bad MP Config Table sig 0x%x and/or checksum 0x%x\n", |
---|
[894a2c91] | 465 | (unsigned)(fps_ptr->cth_ptr), |
---|
[01f2692e] | 466 | sum |
---|
[894a2c91] | 467 | ); |
---|
| 468 | return 1; |
---|
| 469 | } |
---|
| 470 | if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) { |
---|
[01f2692e] | 471 | printk( |
---|
| 472 | " Bad MP Config Table sub-revision # %d\n", |
---|
| 473 | local_cth_ptr->spec_rev |
---|
[894a2c91] | 474 | ); |
---|
| 475 | return 1; |
---|
| 476 | } |
---|
| 477 | if (local_cth_ptr->extended_length) { |
---|
| 478 | sum = (get_checksum(((unsigned)local_cth_ptr) |
---|
| 479 | + local_cth_ptr->base_length, |
---|
| 480 | local_cth_ptr->extended_length) |
---|
| 481 | + local_cth_ptr->extended_checksum) & 0xFF; |
---|
| 482 | if (sum) { |
---|
[01f2692e] | 483 | printk(" Bad Extended MP Config Table checksum 0x%x\n", sum); |
---|
[894a2c91] | 484 | return 1; |
---|
| 485 | } |
---|
| 486 | } |
---|
| 487 | } else if (!fps_ptr->feature_info[0]) { |
---|
[01f2692e] | 488 | printk(" Missing configuration information\n"); |
---|
[894a2c91] | 489 | return 1; |
---|
| 490 | } |
---|
| 491 | |
---|
| 492 | return 0; |
---|
[1d007c60] | 493 | } |
---|
| 494 | |
---|
| 495 | static void |
---|
| 496 | imps_read_bios(imps_fps *fps_ptr) |
---|
| 497 | { |
---|
[894a2c91] | 498 | int apicid; |
---|
| 499 | unsigned cth_start, cth_count; |
---|
| 500 | imps_cth *local_cth_ptr |
---|
| 501 | = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr); |
---|
| 502 | char *str_ptr; |
---|
| 503 | |
---|
[01f2692e] | 504 | printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n", |
---|
| 505 | fps_ptr->spec_rev); |
---|
[894a2c91] | 506 | |
---|
| 507 | /* |
---|
| 508 | * Do all checking of errors which would definitely |
---|
| 509 | * lead to failure of the SMP boot here. |
---|
| 510 | */ |
---|
| 511 | if (imps_bad_bios(fps_ptr)) { |
---|
[01f2692e] | 512 | printk(" Disabling MPS support\n"); |
---|
[894a2c91] | 513 | return; |
---|
| 514 | } |
---|
| 515 | |
---|
| 516 | if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) { |
---|
| 517 | str_ptr = "IMCR and PIC"; |
---|
| 518 | } else { |
---|
| 519 | str_ptr = "Virtual Wire"; |
---|
| 520 | } |
---|
| 521 | if (fps_ptr->cth_ptr) { |
---|
| 522 | imps_lapic_addr = local_cth_ptr->lapic_addr; |
---|
| 523 | } else { |
---|
| 524 | imps_lapic_addr = LAPIC_ADDR_DEFAULT; |
---|
| 525 | } |
---|
[01f2692e] | 526 | printk(" APIC config: \"%s mode\" Local APIC address: 0x%x\n", |
---|
| 527 | str_ptr, imps_lapic_addr); |
---|
[894a2c91] | 528 | if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) { |
---|
[01f2692e] | 529 | printk("Inconsistent Local APIC address, Disabling SMP support\n"); |
---|
[894a2c91] | 530 | return; |
---|
| 531 | } |
---|
| 532 | imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr); |
---|
| 533 | |
---|
| 534 | /* |
---|
| 535 | * Setup primary CPU. |
---|
| 536 | */ |
---|
| 537 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
| 538 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
| 539 | apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID)); |
---|
| 540 | imps_cpu_apic_map[0] = apicid; |
---|
| 541 | imps_apic_cpu_map[apicid] = 0; |
---|
| 542 | |
---|
| 543 | if (fps_ptr->cth_ptr) { |
---|
| 544 | char str1[16], str2[16]; |
---|
| 545 | memcpy(str1, local_cth_ptr->oem_id, 8); |
---|
| 546 | str1[8] = 0; |
---|
| 547 | memcpy(str2, local_cth_ptr->prod_id, 12); |
---|
| 548 | str2[12] = 0; |
---|
[01f2692e] | 549 | printk(" OEM id: %s Product id: %s\n", str1, str2); |
---|
[894a2c91] | 550 | cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth); |
---|
| 551 | cth_count = local_cth_ptr->entry_count; |
---|
| 552 | } else { |
---|
| 553 | *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_ID; |
---|
| 554 | defconfig.ioapic.id |
---|
| 555 | = APIC_ID(*((volatile unsigned *) |
---|
| 556 | (IOAPIC_ADDR_DEFAULT+IOAPIC_RW))); |
---|
| 557 | *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_VER; |
---|
| 558 | defconfig.ioapic.ver |
---|
| 559 | = APIC_VERSION(*((volatile unsigned *) |
---|
| 560 | (IOAPIC_ADDR_DEFAULT+IOAPIC_RW))); |
---|
| 561 | defconfig.proc[apicid].flags |
---|
| 562 | = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT; |
---|
| 563 | defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED; |
---|
| 564 | imps_num_cpus = 2; |
---|
| 565 | if (fps_ptr->feature_info[0] == 1 |
---|
| 566 | || fps_ptr->feature_info[0] == 5) { |
---|
| 567 | memcpy(defconfig.bus[0].bus_type, "ISA ", 6); |
---|
| 568 | } |
---|
| 569 | if (fps_ptr->feature_info[0] == 4 |
---|
| 570 | || fps_ptr->feature_info[0] == 7) { |
---|
| 571 | memcpy(defconfig.bus[0].bus_type, "MCA ", 6); |
---|
| 572 | } |
---|
| 573 | if (fps_ptr->feature_info[0] > 4) { |
---|
| 574 | defconfig.proc[0].apic_ver = 0x10; |
---|
| 575 | defconfig.proc[1].apic_ver = 0x10; |
---|
| 576 | defconfig.bus[1].type = IMPS_BCT_BUS; |
---|
| 577 | } |
---|
| 578 | if (fps_ptr->feature_info[0] == 2) { |
---|
| 579 | defconfig.intin[2].type = 255; |
---|
| 580 | defconfig.intin[13].type = 255; |
---|
| 581 | } |
---|
| 582 | if (fps_ptr->feature_info[0] == 7) { |
---|
| 583 | defconfig.intin[0].type = 255; |
---|
| 584 | } |
---|
| 585 | cth_start = (unsigned) &defconfig; |
---|
| 586 | cth_count = DEF_ENTRIES; |
---|
| 587 | } |
---|
| 588 | imps_read_config_table(cth_start, cth_count); |
---|
| 589 | |
---|
| 590 | /* %%%%% ESB read extended entries here */ |
---|
| 591 | |
---|
| 592 | imps_enabled = 1; |
---|
[1d007c60] | 593 | } |
---|
| 594 | |
---|
| 595 | /* |
---|
| 596 | * Given a region to check, this actually looks for the "MP Floating |
---|
| 597 | * Pointer Structure". The return value indicates if the correct |
---|
| 598 | * signature and checksum for a floating pointer structure of the |
---|
| 599 | * appropriate spec revision was found. If so, then do not search |
---|
| 600 | * further. |
---|
| 601 | * |
---|
| 602 | * NOTE: The memory scan will always be in the bottom 1 MB. |
---|
| 603 | * |
---|
| 604 | * This function presumes that "start" will always be aligned to a 16-bit |
---|
| 605 | * boundary. |
---|
| 606 | * |
---|
| 607 | * Function finished. |
---|
| 608 | */ |
---|
| 609 | static int |
---|
| 610 | imps_scan(unsigned start, unsigned length) |
---|
| 611 | { |
---|
[01f2692e] | 612 | printk("Scanning from 0x%x for %d bytes\n", start, length); |
---|
[894a2c91] | 613 | |
---|
| 614 | while (length > 0) { |
---|
| 615 | imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start); |
---|
| 616 | |
---|
| 617 | if (fps_ptr->sig == IMPS_FPS_SIGNATURE |
---|
| 618 | && fps_ptr->length == 1 |
---|
| 619 | && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4) |
---|
| 620 | && !get_checksum(start, 16)) { |
---|
[01f2692e] | 621 | printk("Found MP Floating Structure Pointer at %x\n", start); |
---|
[894a2c91] | 622 | imps_read_bios(fps_ptr); |
---|
| 623 | return 1; |
---|
| 624 | } |
---|
| 625 | |
---|
| 626 | length -= 16; |
---|
| 627 | start += 16; |
---|
| 628 | } |
---|
| 629 | |
---|
| 630 | return 0; |
---|
[1d007c60] | 631 | } |
---|
| 632 | |
---|
[01f2692e] | 633 | #if !defined(__rtems__) |
---|
[1d007c60] | 634 | /* |
---|
| 635 | * This is the primary function to "force" SMP support, with |
---|
| 636 | * the assumption that you have consecutively numbered APIC ids. |
---|
| 637 | */ |
---|
| 638 | int |
---|
| 639 | imps_force(int ncpus) |
---|
| 640 | { |
---|
[894a2c91] | 641 | int apicid, i; |
---|
| 642 | imps_processor p; |
---|
| 643 | |
---|
[01f2692e] | 644 | printk("Intel MultiProcessor \"Force\" Support\n"); |
---|
[894a2c91] | 645 | |
---|
| 646 | imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000); |
---|
| 647 | imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr); |
---|
| 648 | |
---|
| 649 | /* |
---|
| 650 | * Setup primary CPU. |
---|
| 651 | */ |
---|
| 652 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
| 653 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
| 654 | apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID)); |
---|
| 655 | imps_cpu_apic_map[0] = apicid; |
---|
| 656 | imps_apic_cpu_map[apicid] = 0; |
---|
| 657 | |
---|
| 658 | p.type = 0; |
---|
| 659 | p.apic_ver = 0x10; |
---|
| 660 | p.signature = p.features = 0; |
---|
| 661 | |
---|
| 662 | for (i = 0; i < ncpus; i++) { |
---|
| 663 | if (apicid == i) { |
---|
| 664 | p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT; |
---|
| 665 | } else { |
---|
| 666 | p.flags = IMPS_FLAG_ENABLED; |
---|
| 667 | } |
---|
| 668 | p.apic_id = i; |
---|
| 669 | add_processor(&p); |
---|
| 670 | } |
---|
| 671 | |
---|
| 672 | return imps_num_cpus; |
---|
[1d007c60] | 673 | } |
---|
[01f2692e] | 674 | #endif |
---|
[1d007c60] | 675 | |
---|
| 676 | /* |
---|
| 677 | * This is the primary function for probing for MPS compatible hardware |
---|
| 678 | * and BIOS information. Call this during the early stages of OS startup, |
---|
| 679 | * before memory can be messed up. |
---|
| 680 | * |
---|
| 681 | * The probe looks for the "MP Floating Pointer Structure" at locations |
---|
| 682 | * listed at the top of page 4-2 of the spec. |
---|
| 683 | * |
---|
| 684 | * Environment requirements from the OS to run: |
---|
| 685 | * |
---|
| 686 | * (1) : A non-linear virtual to physical memory mapping is probably OK, |
---|
[894a2c91] | 687 | * as (I think) the structures all fall within page boundaries, |
---|
| 688 | * but a linear mapping is recommended. Currently assumes that |
---|
| 689 | * the mapping will remain identical over time (which should be |
---|
| 690 | * OK since it only accesses memory which shouldn't be munged |
---|
| 691 | * by the OS anyway). |
---|
[1d007c60] | 692 | * (2) : The OS only consumes memory which the BIOS says is OK to use, |
---|
[894a2c91] | 693 | * and not any of the BIOS standard areas (the areas 0x400 to |
---|
| 694 | * 0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical |
---|
| 695 | * RAM). Sometimes a small amount of physical RAM is not |
---|
| 696 | * reported by the BIOS, to be used to store MPS and other |
---|
| 697 | * information. |
---|
[1d007c60] | 698 | * (3) : It must be possible to read the CMOS. |
---|
| 699 | * (4) : There must be between 512K and 640K of lower memory (this is a |
---|
[894a2c91] | 700 | * sanity check). |
---|
[1d007c60] | 701 | * |
---|
| 702 | * Function finished. |
---|
| 703 | */ |
---|
[208cd6b] | 704 | int |
---|
[1d007c60] | 705 | imps_probe(void) |
---|
| 706 | { |
---|
[894a2c91] | 707 | /* |
---|
| 708 | * Determine possible address of the EBDA |
---|
| 709 | */ |
---|
| 710 | unsigned ebda_addr = *((unsigned short *) |
---|
| 711 | PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4; |
---|
| 712 | |
---|
| 713 | /* |
---|
| 714 | * Determine amount of installed lower memory (not *available* |
---|
| 715 | * lower memory). |
---|
| 716 | * |
---|
| 717 | * NOTE: This should work reliably as long as we verify the |
---|
| 718 | * machine is at least a system that could possibly have |
---|
| 719 | * MPS compatibility to begin with. |
---|
| 720 | */ |
---|
| 721 | unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8) |
---|
| 722 | | CMOS_READ_BYTE(CMOS_BASE_MEMORY)) << 10; |
---|
[1d007c60] | 723 | |
---|
| 724 | #ifdef IMPS_DEBUG |
---|
[894a2c91] | 725 | imps_enabled = 0; |
---|
| 726 | imps_num_cpus = 1; |
---|
[1d007c60] | 727 | #endif |
---|
| 728 | |
---|
[894a2c91] | 729 | /* |
---|
| 730 | * Sanity check : if this isn't reasonable, it is almost impossibly |
---|
| 731 | * unlikely to be an MPS compatible machine, so return failure. |
---|
| 732 | */ |
---|
| 733 | if (mem_lower < 512*1024 || mem_lower > 640*1024) { |
---|
| 734 | return 0; |
---|
| 735 | } |
---|
[1d007c60] | 736 | |
---|
[894a2c91] | 737 | if (ebda_addr > mem_lower - 1024 |
---|
| 738 | || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr)) |
---|
[1d007c60] | 739 | * 1024 > mem_lower) { |
---|
[894a2c91] | 740 | ebda_addr = 0; |
---|
| 741 | } |
---|
[1d007c60] | 742 | |
---|
[894a2c91] | 743 | if (((ebda_addr && imps_scan(ebda_addr, 1024)) |
---|
| 744 | || (!ebda_addr && imps_scan(mem_lower - 1024, 1024)) |
---|
| 745 | || imps_scan(0xF0000, 0x10000)) && imps_enabled) { |
---|
| 746 | return imps_num_cpus; |
---|
| 747 | } |
---|
[1d007c60] | 748 | |
---|
[894a2c91] | 749 | /* |
---|
| 750 | * If no BIOS info on MPS hardware is found, then return failure. |
---|
| 751 | */ |
---|
[1d007c60] | 752 | |
---|
[894a2c91] | 753 | return 0; |
---|
[1d007c60] | 754 | } |
---|
| 755 | |
---|
[01f2692e] | 756 | /* |
---|
| 757 | * RTEMS SMP BSP Support |
---|
| 758 | */ |
---|
[b23abb48] | 759 | static void smp_apic_ack(void) |
---|
[01f2692e] | 760 | { |
---|
| 761 | (void) IMPS_LAPIC_READ(LAPIC_SPIV); /* dummy read */ |
---|
| 762 | IMPS_LAPIC_WRITE(LAPIC_EOI, 0 ); /* ACK the interrupt */ |
---|
| 763 | } |
---|
| 764 | |
---|
[4d9bd56] | 765 | static void bsp_inter_processor_interrupt(void *arg) |
---|
[01f2692e] | 766 | { |
---|
[b23abb48] | 767 | (void) arg; |
---|
| 768 | |
---|
[01f2692e] | 769 | smp_apic_ack(); |
---|
| 770 | |
---|
[1a971d8] | 771 | _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get()); |
---|
[01f2692e] | 772 | } |
---|
| 773 | |
---|
[208cd6b] | 774 | void |
---|
| 775 | ipi_install_irq(void) |
---|
[01f2692e] | 776 | { |
---|
[2bdcf4fd] | 777 | rtems_status_code status; |
---|
| 778 | |
---|
| 779 | status = rtems_interrupt_handler_install( |
---|
| 780 | 16, |
---|
| 781 | "smp-imps", |
---|
| 782 | RTEMS_INTERRUPT_UNIQUE, |
---|
[4d9bd56] | 783 | bsp_inter_processor_interrupt, |
---|
[2bdcf4fd] | 784 | NULL |
---|
| 785 | ); |
---|
| 786 | assert(status == RTEMS_SUCCESSFUL); |
---|
[01f2692e] | 787 | } |
---|
| 788 | |
---|
| 789 | #ifdef __SSE__ |
---|
| 790 | extern void enable_sse(void); |
---|
| 791 | #endif |
---|
| 792 | |
---|
| 793 | /* pc386 specific initialization */ |
---|
[8cacceb] | 794 | static void secondary_cpu_initialize(void) |
---|
[01f2692e] | 795 | { |
---|
| 796 | int apicid; |
---|
| 797 | |
---|
| 798 | asm volatile( "lidt IDT_Descriptor" ); |
---|
| 799 | |
---|
| 800 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
| 801 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
| 802 | |
---|
| 803 | #ifdef __SSE__ |
---|
| 804 | enable_sse(); |
---|
| 805 | #endif |
---|
[8cacceb] | 806 | |
---|
[406dd62] | 807 | _SMP_Start_multitasking_on_secondary_processor( _Per_CPU_Get() ); |
---|
[01f2692e] | 808 | } |
---|