1 | /* |
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2 | * This file contains code for displaying the Intel Cpu identification |
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3 | * that has been performed by checkCPUtypeSetCr0 function. |
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4 | */ |
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5 | |
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6 | /* |
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7 | * This file was updated by Joel Sherrill <joel.sherrill@oarcorp.com> |
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8 | * to define more capability bits, pick up more CPU model information, |
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9 | * and add more model strings. --joel (April 2010) |
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10 | * |
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11 | * COPYRIGHT (c) 1998 valette@crf.canon.fr |
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12 | * COPYRIGHT (c) 2010 OAR Corporation |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | /* |
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20 | * Tell us the machine setup.. |
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21 | */ |
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22 | #include <stdio.h> |
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23 | #include <rtems/score/cpu.h> |
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24 | #include <string.h> |
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25 | #include <libcpu/cpuModel.h> |
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26 | #include <rtems/bspIo.h> |
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27 | #include <rtems.h> |
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28 | |
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29 | unsigned char Cx86_step = 0; |
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30 | |
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31 | static const char *Cx86_type[] = { |
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32 | "unknown", "1.3", "1.4", "1.5", "1.6", |
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33 | "2.4", "2.5", "2.6", "2.7 or 3.7", "4.2" |
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34 | }; |
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35 | |
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36 | static const char *i486model(unsigned int nr) |
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37 | { |
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38 | static const char *model[] = { |
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39 | "0","DX","SX","DX/2","4","SX/2","6","DX/2-WB","DX/4","DX/4-WB", |
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40 | "10","11","12","13","Am5x86-WT","Am5x86-WB" |
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41 | }; |
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42 | |
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43 | if (nr < sizeof(model)/sizeof(char *)) |
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44 | return model[nr]; |
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45 | return NULL; |
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46 | } |
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47 | |
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48 | static const char * i586model(unsigned int nr) |
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49 | { |
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50 | static const char *model[] = { |
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51 | "0", "Pentium 60/66","Pentium 75+","OverDrive PODP5V83", |
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52 | "Pentium MMX", NULL, NULL, "Mobile Pentium 75+", |
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53 | "Mobile Pentium MMX" |
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54 | }; |
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55 | if (nr < sizeof(model)/sizeof(char *)) |
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56 | return model[nr]; |
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57 | return NULL; |
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58 | } |
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59 | |
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60 | static const char *Cx86model(void) |
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61 | { |
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62 | unsigned char nr6x86 = 0; |
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63 | static const char *model[] = { |
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64 | "unknown", "6x86", "6x86L", "6x86MX", "MII" |
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65 | }; |
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66 | |
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67 | switch (x86) { |
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68 | case 5: |
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69 | /* cx8 flag only on 6x86L */ |
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70 | nr6x86 = ((x86_capability & (1 << 8)) ? 2 : 1); |
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71 | break; |
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72 | case 6: |
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73 | nr6x86 = 3; |
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74 | break; |
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75 | default: |
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76 | nr6x86 = 0; |
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77 | } |
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78 | |
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79 | /* We must get the stepping number by reading DIR1 */ |
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80 | outport_byte(0x22,0xff); |
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81 | inport_byte(0x23, x86_mask); |
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82 | switch (x86_mask) { |
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83 | case 0x03: |
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84 | Cx86_step = 1; /* 6x86MX Rev 1.3 */ |
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85 | break; |
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86 | case 0x04: |
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87 | Cx86_step = 2; /* 6x86MX Rev 1.4 */ |
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88 | break; |
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89 | case 0x05: |
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90 | Cx86_step = 3; /* 6x86MX Rev 1.5 */ |
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91 | break; |
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92 | case 0x06: |
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93 | Cx86_step = 4; /* 6x86MX Rev 1.6 */ |
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94 | break; |
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95 | case 0x14: |
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96 | Cx86_step = 5; /* 6x86 Rev 2.4 */ |
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97 | break; |
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98 | case 0x15: |
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99 | Cx86_step = 6; /* 6x86 Rev 2.5 */ |
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100 | break; |
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101 | case 0x16: |
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102 | Cx86_step = 7; /* 6x86 Rev 2.6 */ |
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103 | break; |
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104 | case 0x17: |
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105 | Cx86_step = 8; /* 6x86 Rev 2.7 or 3.7 */ |
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106 | break; |
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107 | case 0x22: |
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108 | Cx86_step = 9; /* 6x86L Rev 4.2 */ |
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109 | break; |
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110 | default: |
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111 | Cx86_step = 0; |
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112 | } |
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113 | return model[nr6x86]; |
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114 | } |
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115 | |
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116 | static const char * i686model(unsigned int nr) |
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117 | { |
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118 | static const char *model[] = { |
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119 | "PPro A-step", |
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120 | "Pentium Pro" |
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121 | }; |
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122 | if (nr < sizeof(model)/sizeof(char *)) |
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123 | return model[nr]; |
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124 | return NULL; |
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125 | } |
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126 | |
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127 | struct cpu_model_info { |
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128 | int x86; |
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129 | char *model_names[16]; |
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130 | }; |
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131 | |
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132 | static struct cpu_model_info amd_models[] = { |
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133 | { 4, |
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134 | { NULL, NULL, NULL, "DX/2", NULL, NULL, NULL, "DX/2-WB", "DX/4", |
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135 | "DX/4-WB", NULL, NULL, NULL, NULL, "Am5x86-WT", "Am5x86-WB" }}, |
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136 | { 5, |
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137 | { "K5/SSA5 (PR-75, PR-90, PR-100)", "K5 (PR-120, PR-133)", |
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138 | "K5 (PR-166)", "K5 (PR-200)", NULL, NULL, |
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139 | "K6 (166 - 266)", "K6 (166 - 300)", "K6-2 (200 - 450)", |
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140 | "K6-3D-Plus (200 - 450)", NULL, NULL, NULL, NULL, NULL, NULL }}, |
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141 | }; |
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142 | |
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143 | static const char * AMDmodel(void) |
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144 | { |
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145 | const char *p=NULL; |
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146 | int i; |
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147 | |
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148 | if (x86_model < 16) |
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149 | for (i=0; i<sizeof(amd_models)/sizeof(struct cpu_model_info); i++) |
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150 | if (amd_models[i].x86 == x86) { |
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151 | p = amd_models[i].model_names[(int)x86_model]; |
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152 | break; |
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153 | } |
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154 | return p; |
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155 | } |
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156 | |
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157 | static const char * getmodel(int x86, int model) |
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158 | { |
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159 | const char *p = NULL; |
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160 | static char nbuf[12]; |
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161 | |
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162 | if (strncmp(x86_vendor_id, "Cyrix", 5) == 0) |
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163 | p = Cx86model(); |
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164 | else if(strcmp(x86_vendor_id, "AuthenticAMD")==0) |
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165 | p = AMDmodel(); |
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166 | else { |
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167 | switch (x86) { |
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168 | case 4: |
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169 | p = i486model(model); |
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170 | break; |
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171 | case 5: |
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172 | p = i586model(model); |
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173 | break; |
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174 | case 6: |
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175 | p = i686model(model); |
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176 | break; |
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177 | } |
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178 | } |
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179 | if (p) |
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180 | return p; |
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181 | |
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182 | sprintf(nbuf, "%d", model); |
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183 | return nbuf; |
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184 | } |
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185 | |
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186 | void printCpuInfo(void) |
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187 | { |
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188 | int i,j; |
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189 | static const char *x86_cap_flags[] = { |
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190 | "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", |
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191 | "cx8", "apic", "10", "sep", "mtrr", "pge", "mca", "cmov", |
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192 | "pat", "pse36", "psn", "cflsh", "20", "ds", "acpi", "mmx", |
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193 | "fxsr", "sse", "sse2", "ss", "htt", "tm", "30", "pbe" |
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194 | }; |
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195 | static const char *x86_cap_x_flags[] = { |
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196 | "sse3", "pclmulqdq", "dtes64", "monitor", "ds-cpl", "vmx", "smx", "est", |
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197 | "tm2", "ssse3", "cnxt-id", "11", "12", "cmpxchg16b", "xtpr", "pdcm", |
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198 | "16", "pcid", "dca", "sse4.1", "sse4.2", "x2APIC", "movbe", "popcnt" |
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199 | "24", "aesni", "xsave", "xsave", "avx", "29", "30", "31" |
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200 | }; |
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201 | |
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202 | printk("cpu : %c86\n", x86+'0'); |
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203 | printk("model : %s\n", |
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204 | have_cpuid ? getmodel(x86, x86_model) : "unknown"); |
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205 | if (x86_vendor_id [0] == '\0') |
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206 | strcpy(x86_vendor_id, "unknown"); |
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207 | printk("vendor_id : %s\n", x86_vendor_id); |
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208 | |
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209 | if (x86_mask) { |
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210 | if (strncmp(x86_vendor_id, "Cyrix", 5) != 0) { |
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211 | printk("stepping : %d\n", x86_mask); |
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212 | } |
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213 | else { /* we have a Cyrix */ |
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214 | printk("stepping : %s\n", Cx86_type[Cx86_step]); |
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215 | } |
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216 | } else |
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217 | printk("stepping : unknown\n"); |
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218 | |
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219 | printk("fpu : %s\n", (hard_math ? "yes" : "no")); |
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220 | printk("cpuid : %s\n", (have_cpuid ? "yes" : "no")); |
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221 | printk("flags :"); |
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222 | for ( i = j = 0 ; i < 32 ; i++ ) { |
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223 | if ( x86_capability & (1 << i) ) { |
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224 | if ( j && 0 == (j & 7) ) |
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225 | printk("\n "); |
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226 | printk(" %s", x86_cap_flags[i]); |
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227 | j++; |
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228 | } |
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229 | } |
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230 | printk("\n"); |
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231 | printk("flags (ext.):"); |
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232 | for ( i = j = 0 ; i < 32 ; i++ ) { |
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233 | if ( x86_capability_x & (1 << i) ) { |
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234 | if ( j && 0 == (j & 7) ) |
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235 | printk("\n "); |
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236 | printk(" %s", x86_cap_x_flags[i]); |
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237 | j++; |
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238 | } |
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239 | } |
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240 | printk("\n"); |
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241 | printk( "x86_capability_ebx=0x%08x\n", x86_capability_ebx); |
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242 | printk( "x86_capability_cores=0x%08x\n", x86_capability_cores); |
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243 | } |
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