1 | /** |
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2 | * @file |
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3 | * |
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4 | * Clock Tick Device Driver |
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5 | * |
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6 | * History: |
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7 | * + Original driver was go32 clock by Joel Sherrill |
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8 | * + go32 clock driver hardware code was inserted into new |
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9 | * boilerplate when the pc386 BSP by: |
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10 | * Pedro Miguel Da Cruz Neto Romano <pmcnr@camoes.rnl.ist.utl.pt> |
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11 | * Jose Rufino <ruf@asterix.ist.utl.pt> |
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12 | * + Reworked by Joel Sherrill to use clock driver template. |
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13 | * This removes all boilerplate and leave original hardware |
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14 | * code I developed for the go32 BSP. |
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15 | */ |
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16 | |
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17 | /* |
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18 | * COPYRIGHT (c) 1989-2012. |
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19 | * On-Line Applications Research Corporation (OAR). |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in the file LICENSE in this distribution or at |
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23 | * http://www.rtems.org/license/LICENSE. |
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24 | */ |
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25 | |
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26 | #include <bsp.h> |
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27 | #include <bsp/irq-generic.h> |
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28 | #include <bspopts.h> |
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29 | #include <libcpu/cpuModel.h> |
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30 | #include <assert.h> |
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31 | #include <rtems/timecounter.h> |
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32 | #ifdef RTEMS_SMP |
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33 | #include <rtems/score/smpimpl.h> |
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34 | #endif |
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35 | |
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36 | #define CLOCK_VECTOR 0 |
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37 | |
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38 | volatile uint32_t pc386_microseconds_per_isr; |
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39 | volatile uint32_t pc386_isrs_per_tick; |
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40 | uint32_t pc386_clock_click_count; |
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41 | |
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42 | /* forward declaration */ |
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43 | void Clock_isr(void *param); |
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44 | static void Clock_isr_handler(void *param); |
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45 | |
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46 | /* |
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47 | * Roughly the number of cycles per second. Note that these |
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48 | * will be wildly inaccurate if the chip speed changes due to power saving |
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49 | * or thermal modes. |
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50 | * |
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51 | * NOTE: These are only used when the TSC method is used. |
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52 | */ |
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53 | static uint64_t pc586_tsc_frequency; |
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54 | |
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55 | static struct timecounter pc386_tc; |
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56 | |
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57 | /* this driver may need to count ISRs per tick */ |
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58 | #define CLOCK_DRIVER_ISRS_PER_TICK 1 |
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59 | #define CLOCK_DRIVER_ISRS_PER_TICK_VALUE pc386_isrs_per_tick |
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60 | |
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61 | extern volatile uint32_t Clock_driver_ticks; |
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62 | |
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63 | #define READ_8254( _lsb, _msb ) \ |
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64 | do { outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_LATCH); \ |
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65 | inport_byte(TIMER_CNTR0, _lsb); \ |
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66 | inport_byte(TIMER_CNTR0, _msb); \ |
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67 | } while (0) |
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68 | |
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69 | |
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70 | #ifdef RTEMS_SMP |
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71 | #define Clock_driver_support_at_tick() \ |
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72 | do { \ |
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73 | Processor_mask targets; \ |
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74 | _Processor_mask_Assign(&targets, _SMP_Get_online_processors()); \ |
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75 | _Processor_mask_Clear(&targets, _SMP_Get_current_processor()); \ |
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76 | _SMP_Multicast_action(&targets, Clock_isr, NULL); \ |
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77 | } while (0) |
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78 | #endif |
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79 | |
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80 | static uint32_t pc386_get_timecount_tsc(struct timecounter *tc) |
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81 | { |
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82 | return (uint32_t)rdtsc(); |
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83 | } |
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84 | |
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85 | static uint32_t pc386_get_timecount_i8254(struct timecounter *tc) |
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86 | { |
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87 | uint32_t irqs; |
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88 | uint8_t lsb, msb; |
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89 | rtems_interrupt_lock_context lock_context; |
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90 | |
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91 | /* |
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92 | * Fetch all the data in an interrupt critical section. |
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93 | */ |
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94 | |
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95 | rtems_interrupt_lock_acquire(&rtems_i386_i8254_access_lock, &lock_context); |
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96 | |
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97 | READ_8254(lsb, msb); |
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98 | irqs = Clock_driver_ticks; |
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99 | |
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100 | rtems_interrupt_lock_release(&rtems_i386_i8254_access_lock, &lock_context); |
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101 | |
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102 | return (irqs + 1) * pc386_microseconds_per_isr - ((msb << 8) | lsb); |
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103 | } |
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104 | |
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105 | /* |
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106 | * Calibrate CPU cycles per tick. Interrupts should be disabled. |
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107 | */ |
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108 | static void calibrate_tsc(void) |
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109 | { |
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110 | uint64_t begin_time; |
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111 | uint8_t then_lsb, then_msb, now_lsb, now_msb; |
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112 | uint32_t i; |
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113 | |
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114 | /* |
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115 | * We just reset the timer, so we know we're at the beginning of a tick. |
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116 | */ |
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117 | |
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118 | /* |
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119 | * Count cycles. Watching the timer introduces a several microsecond |
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120 | * uncertaintity, so let it cook for a while and divide by the number of |
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121 | * ticks actually executed. |
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122 | */ |
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123 | |
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124 | begin_time = rdtsc(); |
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125 | |
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126 | for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick; |
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127 | i != 0; --i ) { |
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128 | /* We know we've just completed a tick when timer goes from low to high */ |
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129 | then_lsb = then_msb = 0xff; |
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130 | do { |
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131 | READ_8254(now_lsb, now_msb); |
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132 | if ((then_msb < now_msb) || |
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133 | ((then_msb == now_msb) && (then_lsb < now_lsb))) |
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134 | break; |
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135 | then_lsb = now_lsb; |
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136 | then_msb = now_msb; |
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137 | } while (1); |
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138 | } |
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139 | |
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140 | pc586_tsc_frequency = rdtsc() - begin_time; |
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141 | |
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142 | #if 0 |
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143 | printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_frequency / 1000000)); |
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144 | #endif |
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145 | } |
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146 | |
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147 | static void clockOn(void) |
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148 | { |
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149 | rtems_interrupt_lock_context lock_context; |
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150 | pc386_isrs_per_tick = 1; |
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151 | pc386_microseconds_per_isr = rtems_configuration_get_microseconds_per_tick(); |
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152 | |
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153 | while (US_TO_TICK(pc386_microseconds_per_isr) > 65535) { |
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154 | pc386_isrs_per_tick *= 10; |
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155 | pc386_microseconds_per_isr /= 10; |
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156 | } |
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157 | pc386_clock_click_count = US_TO_TICK(pc386_microseconds_per_isr); |
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158 | |
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159 | #if 0 |
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160 | printk( "configured usecs per tick=%d \n", |
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161 | rtems_configuration_get_microseconds_per_tick() ); |
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162 | printk( "Microseconds per ISR =%d\n", pc386_microseconds_per_isr ); |
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163 | printk( "final ISRs per=%d\n", pc386_isrs_per_tick ); |
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164 | printk( "final timer counts=%d\n", pc386_clock_click_count ); |
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165 | #endif |
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166 | |
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167 | rtems_interrupt_lock_acquire(&rtems_i386_i8254_access_lock, &lock_context); |
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168 | outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_16BIT|TIMER_RATEGEN); |
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169 | outport_byte(TIMER_CNTR0, pc386_clock_click_count >> 0 & 0xff); |
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170 | outport_byte(TIMER_CNTR0, pc386_clock_click_count >> 8 & 0xff); |
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171 | rtems_interrupt_lock_release(&rtems_i386_i8254_access_lock, &lock_context); |
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172 | |
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173 | bsp_interrupt_vector_enable( BSP_PERIODIC_TIMER ); |
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174 | |
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175 | /* |
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176 | * Now calibrate cycles per tick. Do this every time we |
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177 | * turn the clock on in case the CPU clock speed has changed. |
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178 | */ |
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179 | if ( x86_has_tsc() ) |
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180 | calibrate_tsc(); |
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181 | } |
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182 | |
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183 | bool Clock_isr_enabled = false; |
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184 | static void Clock_isr_handler(void *param) |
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185 | { |
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186 | if ( Clock_isr_enabled ) |
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187 | Clock_isr( param ); |
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188 | } |
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189 | |
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190 | void Clock_driver_install_handler(void) |
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191 | { |
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192 | rtems_status_code status; |
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193 | |
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194 | status = rtems_interrupt_handler_install( |
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195 | BSP_PERIODIC_TIMER, |
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196 | "ckinit", |
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197 | RTEMS_INTERRUPT_UNIQUE, |
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198 | Clock_isr_handler, |
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199 | NULL |
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200 | ); |
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201 | assert(status == RTEMS_SUCCESSFUL); |
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202 | clockOn(); |
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203 | } |
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204 | |
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205 | #define Clock_driver_support_set_interrupt_affinity(online_processors) \ |
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206 | do { \ |
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207 | /* FIXME: Is there a way to do this on x86? */ \ |
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208 | (void) online_processors; \ |
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209 | } while (0) |
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210 | |
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211 | void Clock_driver_support_initialize_hardware(void) |
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212 | { |
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213 | bool use_tsc = false; |
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214 | bool use_8254 = false; |
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215 | |
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216 | #if (CLOCK_DRIVER_USE_TSC == 1) |
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217 | use_tsc = true; |
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218 | #endif |
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219 | |
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220 | #if (CLOCK_DRIVER_USE_8254 == 1) |
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221 | use_8254 = true; |
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222 | #endif |
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223 | |
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224 | if ( !use_tsc && !use_8254 ) { |
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225 | if ( x86_has_tsc() ) use_tsc = true; |
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226 | else use_8254 = true; |
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227 | } |
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228 | |
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229 | if ( use_8254 ) { |
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230 | /* printk( "Use 8254\n" ); */ |
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231 | pc386_tc.tc_get_timecount = pc386_get_timecount_i8254; |
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232 | pc386_tc.tc_counter_mask = 0xffffffff; |
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233 | pc386_tc.tc_frequency = TIMER_TICK; |
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234 | } else { |
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235 | /* printk( "Use TSC\n" ); */ |
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236 | pc386_tc.tc_get_timecount = pc386_get_timecount_tsc; |
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237 | pc386_tc.tc_counter_mask = 0xffffffff; |
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238 | pc386_tc.tc_frequency = pc586_tsc_frequency; |
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239 | } |
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240 | |
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241 | pc386_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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242 | rtems_timecounter_install(&pc386_tc); |
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243 | Clock_isr_enabled = true; |
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244 | } |
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245 | |
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246 | #include "../../../shared/dev/clock/clockimpl.h" |
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