[eb7c6a84] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[b62009c3] | 4 | * Clock Tick Device Driver |
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| 5 | * |
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| 6 | * History: |
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| 7 | * + Original driver was go32 clock by Joel Sherrill |
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| 8 | * + go32 clock driver hardware code was inserted into new |
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| 9 | * boilerplate when the pc386 BSP by: |
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| 10 | * Pedro Miguel Da Cruz Neto Romano <pmcnr@camoes.rnl.ist.utl.pt> |
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| 11 | * Jose Rufino <ruf@asterix.ist.utl.pt> |
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| 12 | * + Reworked by Joel Sherrill to use clock driver template. |
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| 13 | * This removes all boilerplate and leave original hardware |
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| 14 | * code I developed for the go32 BSP. |
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[eb7c6a84] | 15 | */ |
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| 16 | |
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| 17 | /* |
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| 18 | * COPYRIGHT (c) 1989-2012. |
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[b62009c3] | 19 | * On-Line Applications Research Corporation (OAR). |
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| 20 | * |
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| 21 | * The license and distribution terms for this file may be |
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| 22 | * found in the file LICENSE in this distribution or at |
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[c499856] | 23 | * http://www.rtems.org/license/LICENSE. |
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[b62009c3] | 24 | */ |
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[7150f00f] | 25 | |
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| 26 | #include <bsp.h> |
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[beefa112] | 27 | #include <bsp/irq-generic.h> |
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[b62009c3] | 28 | #include <bspopts.h> |
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[959f887a] | 29 | #include <libcpu/cpuModel.h> |
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[2bdcf4fd] | 30 | #include <assert.h> |
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[75acd9e] | 31 | #include <rtems/timecounter.h> |
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[1a971d8] | 32 | #ifdef RTEMS_SMP |
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| 33 | #include <rtems/score/smpimpl.h> |
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| 34 | #endif |
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[7150f00f] | 35 | |
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[b62009c3] | 36 | #define CLOCK_VECTOR 0 |
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[7150f00f] | 37 | |
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[b62009c3] | 38 | volatile uint32_t pc386_microseconds_per_isr; |
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| 39 | volatile uint32_t pc386_isrs_per_tick; |
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| 40 | uint32_t pc386_clock_click_count; |
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[7150f00f] | 41 | |
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[eb7c6a84] | 42 | /* forward declaration */ |
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| 43 | void Clock_isr(void *param); |
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[2bdcf4fd] | 44 | static void Clock_isr_handler(void *param); |
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[eb7c6a84] | 45 | |
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[959f887a] | 46 | /* |
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[75acd9e] | 47 | * Roughly the number of cycles per second. Note that these |
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[959f887a] | 48 | * will be wildly inaccurate if the chip speed changes due to power saving |
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| 49 | * or thermal modes. |
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| 50 | * |
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| 51 | * NOTE: These are only used when the TSC method is used. |
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| 52 | */ |
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[75acd9e] | 53 | static uint64_t pc586_tsc_frequency; |
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[7150f00f] | 54 | |
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[75acd9e] | 55 | static struct timecounter pc386_tc; |
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[7150f00f] | 56 | |
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[959f887a] | 57 | /* this driver may need to count ISRs per tick */ |
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[3109857c] | 58 | #define CLOCK_DRIVER_ISRS_PER_TICK 1 |
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| 59 | #define CLOCK_DRIVER_ISRS_PER_TICK_VALUE pc386_isrs_per_tick |
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[7150f00f] | 60 | |
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[75acd9e] | 61 | extern volatile uint32_t Clock_driver_ticks; |
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[ee07b997] | 62 | |
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[959f887a] | 63 | #define READ_8254( _lsb, _msb ) \ |
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| 64 | do { outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_LATCH); \ |
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| 65 | inport_byte(TIMER_CNTR0, _lsb); \ |
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| 66 | inport_byte(TIMER_CNTR0, _msb); \ |
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| 67 | } while (0) |
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| 68 | |
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| 69 | |
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[90d8567] | 70 | #ifdef RTEMS_SMP |
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| 71 | #define Clock_driver_support_at_tick() \ |
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[1a971d8] | 72 | do { \ |
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| 73 | Processor_mask targets; \ |
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| 74 | _Processor_mask_Assign(&targets, _SMP_Get_online_processors()); \ |
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| 75 | _Processor_mask_Clear(&targets, _SMP_Get_current_processor()); \ |
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[c954003] | 76 | _SMP_Multicast_action(&targets, rtems_timecounter_tick, NULL); \ |
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[1a971d8] | 77 | } while (0) |
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[90d8567] | 78 | #endif |
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[7150f00f] | 79 | |
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[75acd9e] | 80 | static uint32_t pc386_get_timecount_tsc(struct timecounter *tc) |
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[67a2288] | 81 | { |
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[75acd9e] | 82 | return (uint32_t)rdtsc(); |
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[959f887a] | 83 | } |
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[359e537] | 84 | |
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[75acd9e] | 85 | static uint32_t pc386_get_timecount_i8254(struct timecounter *tc) |
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[959f887a] | 86 | { |
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[75acd9e] | 87 | uint32_t irqs; |
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[b62009c3] | 88 | uint8_t lsb, msb; |
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[6b54dcb] | 89 | rtems_interrupt_lock_context lock_context; |
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[b62009c3] | 90 | |
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| 91 | /* |
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| 92 | * Fetch all the data in an interrupt critical section. |
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| 93 | */ |
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[6b54dcb] | 94 | |
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| 95 | rtems_interrupt_lock_acquire(&rtems_i386_i8254_access_lock, &lock_context); |
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| 96 | |
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[959f887a] | 97 | READ_8254(lsb, msb); |
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[75acd9e] | 98 | irqs = Clock_driver_ticks; |
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[6b54dcb] | 99 | |
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| 100 | rtems_interrupt_lock_release(&rtems_i386_i8254_access_lock, &lock_context); |
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[b62009c3] | 101 | |
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[75acd9e] | 102 | return (irqs + 1) * pc386_microseconds_per_isr - ((msb << 8) | lsb); |
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[67a2288] | 103 | } |
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| 104 | |
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[959f887a] | 105 | /* |
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| 106 | * Calibrate CPU cycles per tick. Interrupts should be disabled. |
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[4925ab4] | 107 | * Will also set the PIT, so call this before registering the |
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| 108 | * periodic timer for rtems tick generation |
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[959f887a] | 109 | */ |
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| 110 | static void calibrate_tsc(void) |
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| 111 | { |
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| 112 | uint64_t begin_time; |
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[4925ab4] | 113 | uint8_t lsb, msb; |
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| 114 | uint32_t max_timer_value; |
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| 115 | uint32_t last_tick, cur_tick; |
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| 116 | int32_t diff, remaining; |
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| 117 | |
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| 118 | /* Set the timer to free running mode */ |
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| 119 | outport_byte(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_INTTC); |
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| 120 | /* Reset the 16 timer reload value, first LSB, then MSB */ |
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| 121 | outport_byte(TIMER_CNTR0, 0); |
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| 122 | outport_byte(TIMER_CNTR0, 0); |
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| 123 | /* We use the full 16 bit */ |
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| 124 | max_timer_value = 0xffff; |
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| 125 | /* Calibrate for 1s, i.e. TIMER_TICK PIT ticks */ |
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| 126 | remaining = TIMER_TICK; |
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[959f887a] | 127 | |
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| 128 | begin_time = rdtsc(); |
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[4925ab4] | 129 | READ_8254(lsb, msb); |
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| 130 | last_tick = (msb << 8) | lsb; |
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| 131 | while(remaining > 0) { |
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| 132 | READ_8254(lsb, msb); |
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| 133 | cur_tick = (msb << 8) | lsb; |
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| 134 | /* PIT counts down, so subtract cur from last */ |
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| 135 | diff = last_tick - cur_tick; |
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| 136 | last_tick = cur_tick; |
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| 137 | if (diff < 0) { |
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| 138 | diff += max_timer_value; |
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| 139 | } |
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| 140 | remaining -= diff; |
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[959f887a] | 141 | } |
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| 142 | |
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[75acd9e] | 143 | pc586_tsc_frequency = rdtsc() - begin_time; |
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[959f887a] | 144 | |
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[88ef1655] | 145 | #if 0 |
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[4925ab4] | 146 | printk( "CPU clock at %u Hz\n", (uint32_t)(pc586_tsc_frequency )); |
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[959f887a] | 147 | #endif |
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| 148 | } |
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[b62009c3] | 149 | |
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[2bdcf4fd] | 150 | static void clockOn(void) |
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[7150f00f] | 151 | { |
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[4925ab4] | 152 | |
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| 153 | /* |
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| 154 | * First calibrate the TSC. Do this every time we |
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| 155 | * turn the clock on in case the CPU clock speed has changed. |
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| 156 | */ |
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| 157 | if ( x86_has_tsc() ) { |
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| 158 | calibrate_tsc(); |
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| 159 | } |
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| 160 | |
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[6b54dcb] | 161 | rtems_interrupt_lock_context lock_context; |
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[b62009c3] | 162 | pc386_isrs_per_tick = 1; |
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| 163 | pc386_microseconds_per_isr = rtems_configuration_get_microseconds_per_tick(); |
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[67a2288] | 164 | |
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[b62009c3] | 165 | while (US_TO_TICK(pc386_microseconds_per_isr) > 65535) { |
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| 166 | pc386_isrs_per_tick *= 10; |
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| 167 | pc386_microseconds_per_isr /= 10; |
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[67a2288] | 168 | } |
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[b62009c3] | 169 | pc386_clock_click_count = US_TO_TICK(pc386_microseconds_per_isr); |
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| 170 | |
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| 171 | #if 0 |
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[359e537] | 172 | printk( "configured usecs per tick=%d \n", |
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[b62009c3] | 173 | rtems_configuration_get_microseconds_per_tick() ); |
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| 174 | printk( "Microseconds per ISR =%d\n", pc386_microseconds_per_isr ); |
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| 175 | printk( "final ISRs per=%d\n", pc386_isrs_per_tick ); |
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| 176 | printk( "final timer counts=%d\n", pc386_clock_click_count ); |
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| 177 | #endif |
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| 178 | |
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[6b54dcb] | 179 | rtems_interrupt_lock_acquire(&rtems_i386_i8254_access_lock, &lock_context); |
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[b62009c3] | 180 | outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_16BIT|TIMER_RATEGEN); |
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| 181 | outport_byte(TIMER_CNTR0, pc386_clock_click_count >> 0 & 0xff); |
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| 182 | outport_byte(TIMER_CNTR0, pc386_clock_click_count >> 8 & 0xff); |
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[6b54dcb] | 183 | rtems_interrupt_lock_release(&rtems_i386_i8254_access_lock, &lock_context); |
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| 184 | |
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[2220a53] | 185 | bsp_interrupt_vector_enable( BSP_PERIODIC_TIMER ); |
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[b62009c3] | 186 | } |
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[7150f00f] | 187 | |
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[8a7ed82] | 188 | bool Clock_isr_enabled = false; |
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[2bdcf4fd] | 189 | static void Clock_isr_handler(void *param) |
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[8a7ed82] | 190 | { |
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| 191 | if ( Clock_isr_enabled ) |
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[eb7c6a84] | 192 | Clock_isr( param ); |
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[8a7ed82] | 193 | } |
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| 194 | |
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| 195 | void Clock_driver_install_handler(void) |
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| 196 | { |
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[2bdcf4fd] | 197 | rtems_status_code status; |
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| 198 | |
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| 199 | status = rtems_interrupt_handler_install( |
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| 200 | BSP_PERIODIC_TIMER, |
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| 201 | "ckinit", |
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| 202 | RTEMS_INTERRUPT_UNIQUE, |
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| 203 | Clock_isr_handler, |
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| 204 | NULL |
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| 205 | ); |
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| 206 | assert(status == RTEMS_SUCCESSFUL); |
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| 207 | clockOn(); |
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[8a7ed82] | 208 | } |
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| 209 | |
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[90d8567] | 210 | #define Clock_driver_support_set_interrupt_affinity(online_processors) \ |
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| 211 | do { \ |
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| 212 | /* FIXME: Is there a way to do this on x86? */ \ |
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| 213 | (void) online_processors; \ |
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| 214 | } while (0) |
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| 215 | |
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[88ef1655] | 216 | void Clock_driver_support_initialize_hardware(void) |
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[959f887a] | 217 | { |
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| 218 | bool use_tsc = false; |
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| 219 | bool use_8254 = false; |
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[359e537] | 220 | |
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[959f887a] | 221 | #if (CLOCK_DRIVER_USE_TSC == 1) |
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| 222 | use_tsc = true; |
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| 223 | #endif |
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| 224 | |
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| 225 | #if (CLOCK_DRIVER_USE_8254 == 1) |
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| 226 | use_8254 = true; |
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| 227 | #endif |
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[359e537] | 228 | |
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[959f887a] | 229 | if ( !use_tsc && !use_8254 ) { |
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| 230 | if ( x86_has_tsc() ) use_tsc = true; |
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| 231 | else use_8254 = true; |
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| 232 | } |
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| 233 | |
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| 234 | if ( use_8254 ) { |
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[88ef1655] | 235 | /* printk( "Use 8254\n" ); */ |
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[75acd9e] | 236 | pc386_tc.tc_get_timecount = pc386_get_timecount_i8254; |
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| 237 | pc386_tc.tc_counter_mask = 0xffffffff; |
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| 238 | pc386_tc.tc_frequency = TIMER_TICK; |
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[959f887a] | 239 | } else { |
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[88ef1655] | 240 | /* printk( "Use TSC\n" ); */ |
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[75acd9e] | 241 | pc386_tc.tc_get_timecount = pc386_get_timecount_tsc; |
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| 242 | pc386_tc.tc_counter_mask = 0xffffffff; |
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| 243 | pc386_tc.tc_frequency = pc586_tsc_frequency; |
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[959f887a] | 244 | } |
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| 245 | |
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[75acd9e] | 246 | pc386_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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| 247 | rtems_timecounter_install(&pc386_tc); |
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[8a7ed82] | 248 | Clock_isr_enabled = true; |
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[959f887a] | 249 | } |
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[b62009c3] | 250 | |
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[7632906] | 251 | #include "../../../shared/dev/clock/clockimpl.h" |
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