source: rtems/bsps/i386/include/uart.h @ 7632906

5
Last change on this file since 7632906 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 6.1 KB
Line 
1/**
2 * @file
3 * @ingroup i386_uart
4 * @brief i386 UART definitions
5 */
6
7/*
8 * This software is Copyright (C) 1998 by T.sqware - all rights limited
9 * It is provided in to the public domain "as is", can be freely modified
10 * as far as this copyight notice is kept unchanged, but does not imply
11 * an endorsement by T.sqware of the product in which it is included.
12 */
13
14/**
15 * @defgroup i386_uart UART
16 * @ingroup i386_comm
17 * @brief i386 UART definitions
18 * @{
19 */
20
21#ifndef _BSPUART_H
22#define _BSPUART_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
29void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
30void BSP_uart_set_baud(int uart, unsigned long baud);
31void BSP_uart_intr_ctrl(int uart, int cmd);
32void BSP_uart_throttle(int uart);
33void BSP_uart_unthrottle(int uart);
34int  BSP_uart_polled_status(int uart);
35void BSP_uart_polled_write(int uart, int val);
36int  BSP_uart_polled_read(int uart);
37void BSP_uart_termios_set(int uart, void *ttyp);
38int  BSP_uart_termios_read_com1(int uart);
39int  BSP_uart_termios_read_com2(int uart);
40ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len);
41ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len);
42void BSP_uart_termios_isr_com1(void *);
43void BSP_uart_termios_isr_com2(void *);
44void BSP_uart_dbgisr_com1(void);
45void BSP_uart_dbgisr_com2(void);
46extern int BSP_poll_char_via_serial(void);
47extern void BSP_output_char_via_serial(char val);
48extern int BSPConsolePort;
49extern int BSPBaseBaud;
50
51/** @brief
52 * Command values for BSP_uart_intr_ctrl(),
53 * values are strange in order to catch errors
54 * with assert
55 */
56#define BSP_UART_INTR_CTRL_DISABLE  (0)
57#define BSP_UART_INTR_CTRL_GDB      (0xaa) ///< RX only
58#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) ///< Normal operations
59#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) ///< RX & line status
60
61/** @brief Return values for uart_polled_status() */
62#define BSP_UART_STATUS_ERROR    (-1) ///< No character
63#define BSP_UART_STATUS_NOCHAR   (0)  ///< No character
64#define BSP_UART_STATUS_CHAR     (1)  ///< Character present
65#define BSP_UART_STATUS_BREAK    (2)  ///< Break point is detected
66
67/** @brief PC UART definitions */
68#define BSP_UART_COM1            (0)
69#define BSP_UART_COM2            (1)
70
71/** @brief
72 * Base IO for UART
73 */
74
75#define COM1_BASE_IO    0x3F8
76#define COM2_BASE_IO    0x2F8
77
78/** @brief
79 * Offsets from base
80 */
81
82/** @brief DLAB 0 */
83#define RBR  (0)    ///< Rx Buffer Register (read)
84#define THR  (0)    ///< Tx Buffer Register (write)
85#define IER  (1)    ///< Interrupt Enable Register
86
87/** @brief DLAB X */
88#define IIR  (2)    ///< Interrupt Ident Register (read)
89#define FCR  (2)    ///< FIFO Control Register (write)
90#define LCR  (3)    ///< Line Control Register
91#define MCR  (4)    ///< Modem Control Register
92#define LSR  (5)    ///< Line Status Register
93#define MSR  (6)    ///< Modem Status  Register
94#define SCR  (7)    ///< Scratch register
95
96/** @brief DLAB 1 */
97#define DLL  (0)    ///< Divisor Latch, LSB
98#define DLM  (1)    ///< Divisor Latch, MSB
99#define AFR  (2)    ///< Alternate Function register
100
101/** @brief
102 * Interrupt source definition via IIR
103 */
104#define MODEM_STATUS                            0
105#define NO_MORE_INTR                            1
106#define TRANSMITTER_HODING_REGISTER_EMPTY       2
107#define RECEIVER_DATA_AVAIL                     4
108#define RECEIVER_ERROR                          6
109#define CHARACTER_TIMEOUT_INDICATION            12
110
111/** @brief
112 * Bits definition of IER
113 */
114#define RECEIVE_ENABLE          0x1
115#define TRANSMIT_ENABLE         0x2
116#define RECEIVER_LINE_ST_ENABLE 0x4
117#define MODEM_ENABLE            0x8
118#define INTERRUPT_DISABLE       0x0
119
120/** @brief
121 * Bits definition of the Line Status Register (LSR)
122 */
123#define DR      0x01    ///< Data Ready
124#define OE      0x02    ///< Overrun Error
125#define PE      0x04    ///< Parity Error
126#define FE      0x08    ///< Framing Error
127#define BI      0x10    ///< Break Interrupt
128#define THRE    0x20    ///< Transmitter Holding Register Empty
129#define TEMT    0x40    ///< Transmitter Empty
130#define ERFIFO  0x80    ///< Error receive Fifo
131
132/** @brief
133 * Bits definition of the MODEM Control Register (MCR)
134 */
135#define DTR     0x01    ///< Data Terminal Ready
136#define RTS     0x02    ///< Request To Send
137#define OUT_1   0x04    ///< Output 1, (reserved on COMPAQ I/O Board)
138#define OUT_2   0x08    ///< Output 2, Enable Asynchronous Port Interrupts
139#define LB      0x10    ///< Enable Internal Loop Back
140
141/** @brief
142 * Bits definition of the Line Control Register (LCR)
143 */
144#define CHR_5_BITS 0
145#define CHR_6_BITS 1
146#define CHR_7_BITS 2
147#define CHR_8_BITS 3
148
149#define WL      0x03    ///< Word length mask
150#define STB     0x04    ///< 1 Stop Bit, otherwise 2 Stop Bits
151#define PEN     0x08    ///< Parity Enabled
152#define EPS     0x10    ///< Even Parity Select, otherwise Odd
153#define SP      0x20    ///< Stick Parity
154#define BCB     0x40    ///< Break Control Bit
155#define DLAB    0x80    ///< Enable Divisor Latch Access
156
157/** @brief
158 * Bits definition of the MODEM Status Register (MSR)
159 */
160#define DCTS    0x01    ///< Delta Clear To Send
161#define DDSR    0x02    ///< Delta Data Set Ready
162#define TERI    0x04    ///< Trailing Edge Ring Indicator
163#define DDCD    0x08    ///< Delta Carrier Detect Indicator
164#define CTS     0x10    ///< Clear To Send (when loop back is active)
165#define DSR     0x20    ///< Data Set Ready (when loop back is active)
166#define RI      0x40    ///< Ring Indicator (when loop back is active)
167#define DCD     0x80    ///< Data Carrier Detect (when loop back is active)
168
169/** @brief
170 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
171 */
172
173#define FIFO_CTRL   0x01    ///< Set to 1 permit access to other bits
174#define FIFO_EN     0x01    ///< Enable the FIFO
175#define XMIT_RESET  0x02    ///< Transmit FIFO Reset
176#define RCV_RESET   0x04    ///< Receive FIFO Reset
177#define FCR3        0x08    ///< do not understand manual!
178
179#define RECEIVE_FIFO_TRIGGER1   0x0  ///< trigger recieve interrupt after 1 byte
180#define RECEIVE_FIFO_TRIGGER4   0x40 ///< trigger recieve interrupt after 4 byte
181#define RECEIVE_FIFO_TRIGGER8   0x80 ///< trigger recieve interrupt after 8 byte
182#define RECEIVE_FIFO_TRIGGER12  0xc0 ///< trigger recieve interrupt after 12 byte
183#define TRIG_LEVEL              0xc0 ///< Mask for the trigger level
184
185/** @} */
186
187#ifdef __cplusplus
188}
189#endif
190
191#endif /* _BSPUART_H */
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