[52943a24] | 1 | /** |
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| 2 | * @file |
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| 3 | * @ingroup i386_uart |
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| 4 | * @brief i386 UART definitions |
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| 5 | */ |
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| 6 | |
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[0ebbf66] | 7 | /* |
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| 8 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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| 9 | * It is provided in to the public domain "as is", can be freely modified |
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| 10 | * as far as this copyight notice is kept unchanged, but does not imply |
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| 11 | * an endorsement by T.sqware of the product in which it is included. |
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| 12 | */ |
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| 13 | |
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[52943a24] | 14 | /** |
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| 15 | * @defgroup i386_uart UART |
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| 16 | * @ingroup i386_comm |
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| 17 | * @brief i386 UART definitions |
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| 18 | * @{ |
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| 19 | */ |
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| 20 | |
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[0ebbf66] | 21 | #ifndef _BSPUART_H |
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| 22 | #define _BSPUART_H |
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| 23 | |
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[67113c7] | 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |
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[8ad5399] | 28 | void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow); |
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| 29 | void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits); |
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[e6f5358] | 30 | void BSP_uart_set_baud(int uart, unsigned long baud); |
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[0ebbf66] | 31 | void BSP_uart_intr_ctrl(int uart, int cmd); |
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| 32 | void BSP_uart_throttle(int uart); |
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| 33 | void BSP_uart_unthrottle(int uart); |
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| 34 | int BSP_uart_polled_status(int uart); |
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| 35 | void BSP_uart_polled_write(int uart, int val); |
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| 36 | int BSP_uart_polled_read(int uart); |
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| 37 | void BSP_uart_termios_set(int uart, void *ttyp); |
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[caeb33b2] | 38 | int BSP_uart_termios_read_com1(int uart); |
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| 39 | int BSP_uart_termios_read_com2(int uart); |
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[2daa19f] | 40 | ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len); |
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| 41 | ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len); |
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[5b6438a] | 42 | void BSP_uart_termios_isr_com1(void *); |
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| 43 | void BSP_uart_termios_isr_com2(void *); |
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[0ebbf66] | 44 | void BSP_uart_dbgisr_com1(void); |
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| 45 | void BSP_uart_dbgisr_com2(void); |
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[dfddaf1] | 46 | extern int BSP_poll_char_via_serial(void); |
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| 47 | extern void BSP_output_char_via_serial(char val); |
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[0ebbf66] | 48 | extern int BSPConsolePort; |
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| 49 | extern int BSPBaseBaud; |
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[52943a24] | 50 | |
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| 51 | /** @brief |
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[0ebbf66] | 52 | * Command values for BSP_uart_intr_ctrl(), |
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[6128a4a] | 53 | * values are strange in order to catch errors |
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[0ebbf66] | 54 | * with assert |
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| 55 | */ |
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| 56 | #define BSP_UART_INTR_CTRL_DISABLE (0) |
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[52943a24] | 57 | #define BSP_UART_INTR_CTRL_GDB (0xaa) ///< RX only |
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| 58 | #define BSP_UART_INTR_CTRL_ENABLE (0xbb) ///< Normal operations |
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| 59 | #define BSP_UART_INTR_CTRL_TERMIOS (0xcc) ///< RX & line status |
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[0ebbf66] | 60 | |
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[52943a24] | 61 | /** @brief Return values for uart_polled_status() */ |
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| 62 | #define BSP_UART_STATUS_ERROR (-1) ///< No character |
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| 63 | #define BSP_UART_STATUS_NOCHAR (0) ///< No character |
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| 64 | #define BSP_UART_STATUS_CHAR (1) ///< Character present |
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| 65 | #define BSP_UART_STATUS_BREAK (2) ///< Break point is detected |
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[0ebbf66] | 66 | |
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[52943a24] | 67 | /** @brief PC UART definitions */ |
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[0ebbf66] | 68 | #define BSP_UART_COM1 (0) |
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| 69 | #define BSP_UART_COM2 (1) |
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| 70 | |
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[52943a24] | 71 | /** @brief |
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[0ebbf66] | 72 | * Base IO for UART |
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| 73 | */ |
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| 74 | |
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| 75 | #define COM1_BASE_IO 0x3F8 |
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| 76 | #define COM2_BASE_IO 0x2F8 |
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| 77 | |
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[52943a24] | 78 | /** @brief |
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[0ebbf66] | 79 | * Offsets from base |
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| 80 | */ |
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| 81 | |
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[52943a24] | 82 | /** @brief DLAB 0 */ |
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| 83 | #define RBR (0) ///< Rx Buffer Register (read) |
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| 84 | #define THR (0) ///< Tx Buffer Register (write) |
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| 85 | #define IER (1) ///< Interrupt Enable Register |
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| 86 | |
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| 87 | /** @brief DLAB X */ |
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| 88 | #define IIR (2) ///< Interrupt Ident Register (read) |
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| 89 | #define FCR (2) ///< FIFO Control Register (write) |
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| 90 | #define LCR (3) ///< Line Control Register |
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| 91 | #define MCR (4) ///< Modem Control Register |
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| 92 | #define LSR (5) ///< Line Status Register |
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| 93 | #define MSR (6) ///< Modem Status Register |
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| 94 | #define SCR (7) ///< Scratch register |
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| 95 | |
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| 96 | /** @brief DLAB 1 */ |
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| 97 | #define DLL (0) ///< Divisor Latch, LSB |
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| 98 | #define DLM (1) ///< Divisor Latch, MSB |
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| 99 | #define AFR (2) ///< Alternate Function register |
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| 100 | |
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| 101 | /** @brief |
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[0ebbf66] | 102 | * Interrupt source definition via IIR |
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| 103 | */ |
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| 104 | #define MODEM_STATUS 0 |
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| 105 | #define NO_MORE_INTR 1 |
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| 106 | #define TRANSMITTER_HODING_REGISTER_EMPTY 2 |
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| 107 | #define RECEIVER_DATA_AVAIL 4 |
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| 108 | #define RECEIVER_ERROR 6 |
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| 109 | #define CHARACTER_TIMEOUT_INDICATION 12 |
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| 110 | |
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[52943a24] | 111 | /** @brief |
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[0ebbf66] | 112 | * Bits definition of IER |
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| 113 | */ |
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| 114 | #define RECEIVE_ENABLE 0x1 |
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| 115 | #define TRANSMIT_ENABLE 0x2 |
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| 116 | #define RECEIVER_LINE_ST_ENABLE 0x4 |
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| 117 | #define MODEM_ENABLE 0x8 |
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| 118 | #define INTERRUPT_DISABLE 0x0 |
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| 119 | |
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[52943a24] | 120 | /** @brief |
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[0ebbf66] | 121 | * Bits definition of the Line Status Register (LSR) |
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| 122 | */ |
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[52943a24] | 123 | #define DR 0x01 ///< Data Ready |
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| 124 | #define OE 0x02 ///< Overrun Error |
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| 125 | #define PE 0x04 ///< Parity Error |
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| 126 | #define FE 0x08 ///< Framing Error |
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| 127 | #define BI 0x10 ///< Break Interrupt |
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| 128 | #define THRE 0x20 ///< Transmitter Holding Register Empty |
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| 129 | #define TEMT 0x40 ///< Transmitter Empty |
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| 130 | #define ERFIFO 0x80 ///< Error receive Fifo |
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| 131 | |
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| 132 | /** @brief |
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[0ebbf66] | 133 | * Bits definition of the MODEM Control Register (MCR) |
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| 134 | */ |
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[52943a24] | 135 | #define DTR 0x01 ///< Data Terminal Ready |
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| 136 | #define RTS 0x02 ///< Request To Send |
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| 137 | #define OUT_1 0x04 ///< Output 1, (reserved on COMPAQ I/O Board) |
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| 138 | #define OUT_2 0x08 ///< Output 2, Enable Asynchronous Port Interrupts |
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| 139 | #define LB 0x10 ///< Enable Internal Loop Back |
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[0ebbf66] | 140 | |
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[52943a24] | 141 | /** @brief |
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[0ebbf66] | 142 | * Bits definition of the Line Control Register (LCR) |
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| 143 | */ |
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| 144 | #define CHR_5_BITS 0 |
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| 145 | #define CHR_6_BITS 1 |
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| 146 | #define CHR_7_BITS 2 |
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| 147 | #define CHR_8_BITS 3 |
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| 148 | |
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[52943a24] | 149 | #define WL 0x03 ///< Word length mask |
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| 150 | #define STB 0x04 ///< 1 Stop Bit, otherwise 2 Stop Bits |
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| 151 | #define PEN 0x08 ///< Parity Enabled |
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| 152 | #define EPS 0x10 ///< Even Parity Select, otherwise Odd |
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| 153 | #define SP 0x20 ///< Stick Parity |
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| 154 | #define BCB 0x40 ///< Break Control Bit |
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| 155 | #define DLAB 0x80 ///< Enable Divisor Latch Access |
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[0ebbf66] | 156 | |
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[52943a24] | 157 | /** @brief |
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[0ebbf66] | 158 | * Bits definition of the MODEM Status Register (MSR) |
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| 159 | */ |
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[52943a24] | 160 | #define DCTS 0x01 ///< Delta Clear To Send |
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| 161 | #define DDSR 0x02 ///< Delta Data Set Ready |
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| 162 | #define TERI 0x04 ///< Trailing Edge Ring Indicator |
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| 163 | #define DDCD 0x08 ///< Delta Carrier Detect Indicator |
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| 164 | #define CTS 0x10 ///< Clear To Send (when loop back is active) |
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| 165 | #define DSR 0x20 ///< Data Set Ready (when loop back is active) |
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| 166 | #define RI 0x40 ///< Ring Indicator (when loop back is active) |
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| 167 | #define DCD 0x80 ///< Data Carrier Detect (when loop back is active) |
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| 168 | |
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| 169 | /** @brief |
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[0ebbf66] | 170 | * Bits definition of the FIFO Control Register : WD16C552 or NS16550 |
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| 171 | */ |
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| 172 | |
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[52943a24] | 173 | #define FIFO_CTRL 0x01 ///< Set to 1 permit access to other bits |
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| 174 | #define FIFO_EN 0x01 ///< Enable the FIFO |
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| 175 | #define XMIT_RESET 0x02 ///< Transmit FIFO Reset |
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| 176 | #define RCV_RESET 0x04 ///< Receive FIFO Reset |
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| 177 | #define FCR3 0x08 ///< do not understand manual! |
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| 178 | |
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| 179 | #define RECEIVE_FIFO_TRIGGER1 0x0 ///< trigger recieve interrupt after 1 byte |
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| 180 | #define RECEIVE_FIFO_TRIGGER4 0x40 ///< trigger recieve interrupt after 4 byte |
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| 181 | #define RECEIVE_FIFO_TRIGGER8 0x80 ///< trigger recieve interrupt after 8 byte |
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| 182 | #define RECEIVE_FIFO_TRIGGER12 0xc0 ///< trigger recieve interrupt after 12 byte |
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| 183 | #define TRIG_LEVEL 0xc0 ///< Mask for the trigger level |
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| 184 | |
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| 185 | /** @} */ |
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[0ebbf66] | 186 | |
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[67113c7] | 187 | #ifdef __cplusplus |
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| 188 | } |
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| 189 | #endif |
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| 190 | |
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[0ebbf66] | 191 | #endif /* _BSPUART_H */ |
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