1 | /* Support for Blackfin interrupt controller |
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2 | * |
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3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | |
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12 | #include <rtems.h> |
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13 | #include <rtems/libio.h> |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <libcpu/cecRegs.h> |
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17 | #include <libcpu/sicRegs.h> |
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18 | #include <string.h> |
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19 | #include <libcpu/interrupt.h> |
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20 | |
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21 | |
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22 | static struct { |
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23 | uint32_t mask; |
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24 | bfin_isr_t *head; |
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25 | } vectors[CEC_INTERRUPT_COUNT]; |
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26 | |
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27 | static uint32_t globalMask; |
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28 | |
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29 | |
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30 | static rtems_isr interruptHandler(rtems_vector_number vector) { |
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31 | bfin_isr_t *isr; |
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32 | uint32_t sourceMask; |
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33 | |
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34 | vector -= CEC_INTERRUPT_BASE_VECTOR; |
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35 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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36 | isr = vectors[vector].head; |
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37 | sourceMask = *(uint32_t volatile *) SIC_ISR & |
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38 | *(uint32_t volatile *) SIC_IMASK; |
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39 | while (isr) { |
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40 | if (sourceMask & isr->mask) { |
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41 | isr->isr(isr->source); |
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42 | sourceMask = *(uint32_t volatile *) SIC_ISR & |
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43 | *(uint32_t volatile *) SIC_IMASK; |
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44 | } |
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45 | isr = isr->next; |
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46 | } |
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47 | } |
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48 | } |
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49 | |
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50 | void bfin_interrupt_init(void) { |
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51 | int source; |
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52 | int vector; |
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53 | uint32_t r; |
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54 | int i; |
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55 | int j; |
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56 | |
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57 | globalMask = ~(uint32_t) 0; |
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58 | *(uint32_t volatile *) SIC_IMASK = 0; |
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59 | memset(vectors, 0, sizeof(vectors)); |
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60 | /* build mask showing what SIC sources drive each CEC vector */ |
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61 | source = 0; |
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62 | for (i = 0; i < SIC_IAR_COUNT; i++) { |
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63 | r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); |
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64 | for (j = 0; j < 8; j++) { |
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65 | vector = r & 0x0f; |
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66 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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67 | if (vectors[vector].mask == 0) |
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68 | /* install our local handler */ |
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69 | set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); |
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70 | vectors[vector].mask |= (1 << source); |
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71 | } |
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72 | r >>= 4; |
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73 | source++; |
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74 | } |
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75 | } |
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76 | } |
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77 | |
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78 | /* modify SIC_IMASK based on ISR list for a particular CEC vector */ |
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79 | static void setMask(int vector) { |
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80 | bfin_isr_t *isr; |
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81 | uint32_t mask; |
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82 | uint32_t r; |
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83 | |
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84 | mask = 0; |
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85 | isr = vectors[vector].head; |
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86 | while (isr) { |
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87 | mask |= isr->mask; |
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88 | isr = isr->next; |
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89 | } |
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90 | r = *(uint32_t volatile *) SIC_IMASK; |
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91 | r &= ~vectors[vector].mask; |
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92 | r |= mask; |
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93 | r &= globalMask; |
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94 | *(uint32_t volatile *) SIC_IMASK = r; |
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95 | } |
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96 | |
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97 | /* add an ISR to the list for whichever vector it belongs to */ |
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98 | void bfin_interrupt_register(bfin_isr_t *isr) { |
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99 | bfin_isr_t *walk; |
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100 | rtems_interrupt_level isrLevel; |
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101 | |
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102 | /* find the appropriate vector */ |
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103 | for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++) |
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104 | if (vectors[isr->vector].mask & (1 << isr->source)) |
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105 | break; |
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106 | if (isr->vector < CEC_INTERRUPT_COUNT) { |
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107 | isr->next = NULL; |
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108 | isr->mask = 0; |
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109 | rtems_interrupt_disable(isrLevel); |
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110 | /* find the current end of the list */ |
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111 | walk = vectors[isr->vector].head; |
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112 | while (walk && walk->next) |
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113 | walk = walk->next; |
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114 | /* append new isr to list */ |
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115 | if (walk) |
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116 | walk->next = isr; |
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117 | else |
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118 | vectors[isr->vector].head = isr; |
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119 | rtems_interrupt_enable(isrLevel); |
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120 | } else |
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121 | /* we failed, but make vector a legal value so other calls into |
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122 | this module with this isr descriptor won't do anything bad */ |
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123 | isr->vector = 0; |
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124 | } |
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125 | |
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126 | void bfin_interrupt_unregister(bfin_isr_t *isr) { |
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127 | bfin_isr_t *walk, *prev; |
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128 | rtems_interrupt_level isrLevel; |
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129 | |
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130 | rtems_interrupt_disable(isrLevel); |
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131 | walk = vectors[isr->vector].head; |
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132 | prev = NULL; |
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133 | /* find this isr in our list */ |
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134 | while (walk && walk != isr) { |
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135 | prev = walk; |
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136 | walk = walk->next; |
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137 | } |
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138 | if (walk) { |
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139 | /* if found, remove it */ |
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140 | if (prev) |
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141 | prev->next = walk->next; |
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142 | else |
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143 | vectors[isr->vector].head = walk->next; |
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144 | /* fix up SIC_IMASK if necessary */ |
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145 | setMask(isr->vector); |
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146 | } |
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147 | rtems_interrupt_enable(isrLevel); |
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148 | } |
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149 | |
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150 | void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) { |
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151 | rtems_interrupt_level isrLevel; |
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152 | |
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153 | rtems_interrupt_disable(isrLevel); |
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154 | isr->mask = enable ? (1 << isr->source) : 0; |
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155 | setMask(isr->vector); |
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156 | rtems_interrupt_enable(isrLevel); |
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157 | } |
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158 | |
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159 | void bfin_interrupt_enable_all(int source, bool enable) { |
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160 | rtems_interrupt_level isrLevel; |
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161 | int vector; |
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162 | bfin_isr_t *walk; |
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163 | |
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164 | for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) |
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165 | if (vectors[vector].mask & (1 << source)) |
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166 | break; |
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167 | if (vector < CEC_INTERRUPT_COUNT) { |
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168 | rtems_interrupt_disable(isrLevel); |
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169 | walk = vectors[vector].head; |
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170 | while (walk) { |
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171 | walk->mask = enable ? (1 << source) : 0; |
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172 | walk = walk->next; |
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173 | } |
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174 | setMask(vector); |
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175 | rtems_interrupt_enable(isrLevel); |
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176 | } |
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177 | } |
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178 | |
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179 | void bfin_interrupt_enable_global(int source, bool enable) { |
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180 | int vector; |
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181 | rtems_interrupt_level isrLevel; |
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182 | |
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183 | for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) |
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184 | if (vectors[vector].mask & (1 << source)) |
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185 | break; |
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186 | if (vector < CEC_INTERRUPT_COUNT) { |
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187 | rtems_interrupt_disable(isrLevel); |
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188 | if (enable) |
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189 | globalMask |= 1 << source; |
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190 | else |
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191 | globalMask &= ~(1 << source); |
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192 | setMask(vector); |
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193 | rtems_interrupt_enable(isrLevel); |
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194 | } |
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195 | } |
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196 | |
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