1 | /* SPI driver for Blackfin |
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2 | * |
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3 | * Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #include <stdlib.h> |
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12 | #include <bsp.h> |
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13 | #include <rtems/error.h> |
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14 | #include <rtems/bspIo.h> |
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15 | #include <errno.h> |
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16 | #include <rtems/libi2c.h> |
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17 | #include <libcpu/spiRegs.h> |
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18 | #include <libcpu/spi.h> |
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19 | |
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20 | |
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21 | #ifndef BFIN_REG16 |
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22 | #define BFIN_REG16(base, offset) \ |
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23 | (*((uint16_t volatile *) ((uint8_t *)(base) + (offset)))) |
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24 | #endif |
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25 | |
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26 | |
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27 | static bfin_spi_state_t *bfin_spi; |
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28 | |
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29 | |
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30 | void bfin_spi_isr(int v) { |
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31 | bfin_spi_state_t *state; |
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32 | uint16_t r; |
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33 | |
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34 | state = bfin_spi; |
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35 | if (state->len > state->bytes_per_word) { |
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36 | if (state->wr_ptr) { |
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37 | if (state->bytes_per_word == 2) |
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38 | r = *(uint16_t *) state->wr_ptr; |
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39 | else |
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40 | r = (uint16_t) *state->wr_ptr; |
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41 | state->wr_ptr += state->bytes_per_word; |
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42 | } else |
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43 | r = state->idle_pattern; |
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44 | BFIN_REG16(state->base, SPI_TDBR_OFFSET) = r; |
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45 | } |
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46 | state->len -= state->bytes_per_word; |
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47 | if (state->len <= 0) { |
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48 | /* |
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49 | The transfers are done, so I don't want to kick off another |
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50 | transfer or get any more interrupts. Reading the last word from |
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51 | SPI_SHADOW instead of SPI_RDBR should prevent it from triggering |
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52 | another transfer, but that doesn't clear the interrupt flag. I |
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53 | could mask the interrupt in the SIC, but that would preclude ever |
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54 | using the DMA channel that shares the interrupt independently (and |
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55 | they might just share it with something more important in some other |
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56 | member of the Blackfin family). And who knows what problems it |
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57 | might cause in this code potentially dealing with that still pended |
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58 | interrupt at the beginning of the next transfer. |
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59 | |
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60 | So instead I disable the SPI interface, read the data from RDBR |
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61 | (thus clearing the interrupt but not triggering another transfer |
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62 | since the interface is disabled), then re-eanble the interface. |
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63 | This has the problem that the bf537 tri-states the SPI signals |
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64 | while the interface is disabled. Either adding pull-ups on at |
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65 | least the chip select signals, or using GPIOs for them so they're |
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66 | not controlled by the SPI module, would be correct fixes for that |
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67 | (really pull-ups/downs should be added to the SPI CLK and MOSI |
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68 | signals as well to insure they cannot float into some region that |
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69 | causes input structures to consume excessive power). Or they can |
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70 | all be left alone, assuming that there's enough capacitance on the |
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71 | lines to prevent any problems for the short time they're being left |
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72 | disabled. |
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73 | |
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74 | An alternative approach I attempted involved switching TIMOD |
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75 | between RDBR and TDBR when starting and finishing a transfer, but |
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76 | I didn't get anywhere with that. In my limited testing TIMOD TDBR |
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77 | wasn't behaving as I expected it to, but maybe with more |
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78 | experimentation I'd find some solution there. However I'm out |
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79 | of time for this project, at least for now. |
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80 | */ |
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81 | |
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82 | BFIN_REG16(state->base, SPI_CTL_OFFSET) &= ~SPI_CTL_SPE; |
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83 | r = BFIN_REG16(state->base, SPI_RDBR_OFFSET); |
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84 | BFIN_REG16(state->base, SPI_CTL_OFFSET) |= SPI_CTL_SPE; |
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85 | rtems_semaphore_release(state->sem); |
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86 | } else |
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87 | r = BFIN_REG16(state->base, SPI_RDBR_OFFSET); |
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88 | |
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89 | if (state->rd_ptr) { |
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90 | if (state->bytes_per_word == 2) |
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91 | *(uint16_t *) state->rd_ptr = r; |
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92 | else |
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93 | *state->rd_ptr = (uint8_t) r; |
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94 | state->rd_ptr += state->bytes_per_word; |
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95 | } |
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96 | } |
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97 | |
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98 | static rtems_status_code setTFRMode(rtems_libi2c_bus_t *bus, |
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99 | const rtems_libi2c_tfr_mode_t *tfrMode) { |
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100 | rtems_status_code result; |
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101 | bfin_spi_state_t *state; |
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102 | uint32_t divisor; |
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103 | uint16_t ctrl; |
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104 | |
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105 | result = RTEMS_SUCCESSFUL; |
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106 | state = &((bfin_spi_bus_t *) bus)->p; |
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107 | |
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108 | if (result == RTEMS_SUCCESSFUL) { |
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109 | if (tfrMode->bits_per_char != 8 && |
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110 | tfrMode->bits_per_char != 16) |
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111 | result = RTEMS_INVALID_NUMBER; |
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112 | if (tfrMode->baudrate <= 0) |
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113 | result = RTEMS_INVALID_NUMBER; |
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114 | } |
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115 | if (result == RTEMS_SUCCESSFUL) { |
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116 | divisor = (SCLK / 2 + tfrMode->baudrate - 1) / |
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117 | tfrMode->baudrate; |
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118 | if (divisor < 2) |
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119 | divisor = 2; |
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120 | else if (divisor > 65535) |
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121 | result = RTEMS_INVALID_NUMBER; |
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122 | } |
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123 | if (result == RTEMS_SUCCESSFUL) { |
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124 | state->idle_pattern = (uint16_t) tfrMode->idle_char; |
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125 | state->bytes_per_word = (tfrMode->bits_per_char > 8) ? 2 : 1; |
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126 | BFIN_REG16(state->base, SPI_BAUD_OFFSET) = divisor; |
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127 | ctrl = BFIN_REG16(state->base, SPI_CTL_OFFSET); |
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128 | if (tfrMode->lsb_first) |
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129 | ctrl |= SPI_CTL_LSBF; |
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130 | else |
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131 | ctrl &= ~SPI_CTL_LSBF; |
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132 | if (tfrMode->bits_per_char > 8) |
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133 | ctrl |= SPI_CTL_SIZE; |
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134 | else |
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135 | ctrl &= ~SPI_CTL_SIZE; |
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136 | if (tfrMode->clock_inv) |
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137 | ctrl |= SPI_CTL_CPOL; |
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138 | else |
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139 | ctrl &= ~SPI_CTL_CPOL; |
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140 | if (tfrMode->clock_phs) |
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141 | ctrl |= SPI_CTL_CPHA; |
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142 | else |
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143 | ctrl &= ~SPI_CTL_CPHA; |
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144 | BFIN_REG16(state->base, SPI_CTL_OFFSET) = ctrl; |
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145 | } |
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146 | |
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147 | return result; |
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148 | } |
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149 | |
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150 | static int readWrite(rtems_libi2c_bus_t *bus, uint8_t *rdBuf, |
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151 | const uint8_t *wrBuf, int len) { |
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152 | rtems_status_code result; |
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153 | bfin_spi_state_t *state; |
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154 | uint16_t r; |
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155 | |
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156 | result = RTEMS_SUCCESSFUL; |
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157 | state = &((bfin_spi_bus_t *) bus)->p; |
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158 | |
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159 | if (len) { |
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160 | state->rd_ptr = rdBuf; |
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161 | state->wr_ptr = wrBuf; |
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162 | state->len = len; |
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163 | if (state->wr_ptr) { |
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164 | if (state->bytes_per_word == 2) |
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165 | r = *(uint16_t *) state->wr_ptr; |
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166 | else |
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167 | r = (uint16_t) *state->wr_ptr; |
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168 | state->wr_ptr += state->bytes_per_word; |
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169 | } else |
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170 | r = state->idle_pattern; |
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171 | BFIN_REG16(state->base, SPI_TDBR_OFFSET) = r; |
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172 | BFIN_REG16(state->base, SPI_RDBR_OFFSET); /* trigger */ |
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173 | /* wait until done */ |
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174 | do { |
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175 | result = rtems_semaphore_obtain(state->sem, RTEMS_WAIT, 100); |
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176 | } while (result == RTEMS_SUCCESSFUL && state->len > 0); |
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177 | } |
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178 | |
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179 | return (result == RTEMS_SUCCESSFUL) ? len : -result; |
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180 | } |
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181 | |
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182 | |
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183 | rtems_status_code bfin_spi_init(rtems_libi2c_bus_t *bus) { |
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184 | rtems_status_code result; |
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185 | bfin_spi_state_t *state; |
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186 | |
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187 | state = &((bfin_spi_bus_t *) bus)->p; |
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188 | |
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189 | BFIN_REG16(state->base, SPI_CTL_OFFSET) = SPI_CTL_SPE | |
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190 | SPI_CTL_MSTR | |
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191 | SPI_CTL_CPHA | |
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192 | SPI_CTL_TIMOD_RDBR; |
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193 | |
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194 | result = rtems_semaphore_create(rtems_build_name('s','p','i','s'), |
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195 | 0, |
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196 | RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE, |
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197 | 0, |
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198 | &state->sem); |
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199 | if (result == RTEMS_SUCCESSFUL) |
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200 | bfin_spi = state; /* for isr */ |
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201 | |
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202 | return result; |
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203 | } |
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204 | |
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205 | rtems_status_code bfin_spi_send_start(rtems_libi2c_bus_t *bus) { |
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206 | |
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207 | return RTEMS_SUCCESSFUL; |
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208 | } |
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209 | |
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210 | int bfin_spi_read_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len) { |
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211 | |
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212 | return readWrite(bus, buf, NULL, len); |
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213 | } |
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214 | |
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215 | int bfin_spi_write_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len) { |
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216 | |
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217 | return readWrite(bus, NULL, buf, len); |
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218 | } |
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219 | |
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220 | int bfin_spi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) { |
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221 | int result; |
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222 | |
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223 | result = -RTEMS_NOT_DEFINED; |
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224 | switch(cmd) { |
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225 | case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: |
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226 | result = -setTFRMode(bus, (const rtems_libi2c_tfr_mode_t *) arg); |
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227 | break; |
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228 | case RTEMS_LIBI2C_IOCTL_READ_WRITE: |
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229 | result = readWrite(bus, |
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230 | ((rtems_libi2c_read_write_t *) arg)->rd_buf, |
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231 | ((rtems_libi2c_read_write_t *) arg)->wr_buf, |
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232 | ((rtems_libi2c_read_write_t *) arg)->byte_cnt); |
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233 | break; |
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234 | default: |
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235 | break; |
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236 | } |
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237 | |
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238 | return result; |
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239 | } |
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240 | |
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