source: rtems/bsps/bfin/include/libcpu/twiRegs.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*  Blackfin Two Wire Interface Registers
2 *
3 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 *             written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _twiRegs_h_
12#define _twiRegs_h_
13
14
15/* register addresses */
16
17#define TWI_CLKDIV_OFFSET                             0x0000
18#define TWI_CONTROL_OFFSET                            0x0004
19#define TWI_SLAVE_CTL_OFFSET                          0x0008
20#define TWI_SLAVE_STAT_OFFSET                         0x000c
21#define TWI_SLAVE_ADDR_OFFSET                         0x0010
22#define TWI_MASTER_CTL_OFFSET                         0x0014
23#define TWI_MASTER_STAT_OFFSET                        0x0018
24#define TWI_MASTER_ADDR_OFFSET                        0x001c
25#define TWI_INT_STAT_OFFSET                           0x0020
26#define TWI_INT_MASK_OFFSET                           0x0024
27#define TWI_FIFO_CTL_OFFSET                           0x0028
28#define TWI_FIFO_STAT_OFFSET                          0x002c
29#define TWI_XMT_DATA8_OFFSET                          0x0080
30#define TWI_XMT_DATA16_OFFSET                         0x0084
31#define TWI_RCV_DATA8_OFFSET                          0x0088
32#define TWI_RCV_DATA16_OFFSET                         0x008c
33
34
35/* register fields */
36
37#define TWI_CLKDIV_CLKHI_MASK                         0xff00
38#define TWI_CLKDIV_CLKHI_SHIFT                             8
39#define TWI_CLKDIV_CLKLOW_MASK                        0x00ff
40#define TWI_CLKDIV_CLKLOW_SHIFT                            0
41
42#define TWI_CONTROL_SCCB                              0x0200
43#define TWI_CONTROL_TWI_ENA                           0x0080
44#define TWI_CONTROL_PRESCALE_MASK                     0x007f
45#define TWI_CONTROL_PRESCALE_SHIFT                         0
46
47#define TWI_SLAVE_CTL_GEN                             0x0010
48#define TWI_SLAVE_CTL_NAK                             0x0008
49#define TWI_SLAVE_CTL_STDVAL                          0x0004
50#define TWI_SLAVE_CTL_SEN                             0x0001
51
52#define TWI_SLAVE_STAT_GCALL                          0x0002
53#define TWI_SLAVE_STAT_SDIR                           0x0001
54
55#define TWI_SLAVE_ADDR_SADDR_MASK                     0x007f
56#define TWI_SLAVE_ADDR_SADDR_SHIFT                         0
57
58#define TWI_MASTER_CTL_SCLOVR                         0x8000
59#define TWI_MASTER_CTL_SDAOVR                         0x4000
60#define TWI_MASTER_CTL_DCNT_MASK                      0x3fc0
61#define TWI_MASTER_CTL_DCNT_SHIFT                          6
62#define TWI_MASTER_CTL_RSTART                         0x0020
63#define TWI_MASTER_CTL_STOP                           0x0010
64#define TWI_MASTER_CTL_FAST                           0x0008
65#define TWI_MASTER_CTL_MDIR                           0x0004
66#define TWI_MASTER_CTL_MEN                            0x0001
67
68#define TWI_MASTER_STAT_BUSBUSY                       0x0100
69#define TWI_MASTER_STAT_SCLSEN                        0x0080
70#define TWI_MASTER_STAT_SDASEN                        0x0040
71#define TWI_MASTER_STAT_BUFWRERR                      0x0020
72#define TWI_MASTER_STAT_BUFRDERR                      0x0010
73#define TWI_MASTER_STAT_DNAK                          0x0008
74#define TWI_MASTER_STAT_ANAK                          0x0004
75#define TWI_MASTER_STAT_LOSTARB                       0x0002
76#define TWI_MASTER_STAT_MPROG                         0x0001
77
78#define TWI_MASTER_ADDR_MADDR_MASK                    0x007f
79#define TWI_MASTER_ADDR_MADDR_SHIFT                        0
80
81#define TWI_INT_STAT_RCVSERV                          0x0080
82#define TWI_INT_STAT_XMTSERV                          0x0040
83#define TWI_INT_STAT_MERR                             0x0020
84#define TWI_INT_STAT_MCOMP                            0x0010
85#define TWI_INT_STAT_SOVF                             0x0008
86#define TWI_INT_STAT_SERR                             0x0004
87#define TWI_INT_STAT_SCOMP                            0x0002
88#define TWI_INT_STAT_SINIT                            0x0001
89
90#define TWI_INT_MASK_RCVSERVM                         0x0080
91#define TWI_INT_MASK_XMTSERVM                         0x0040
92#define TWI_INT_MASK_MERRM                            0x0020
93#define TWI_INT_MASK_MCOMPM                           0x0010
94#define TWI_INT_MASK_SOVFM                            0x0008
95#define TWI_INT_MASK_SERRM                            0x0004
96#define TWI_INT_MASK_SCOMPM                           0x0002
97#define TWI_INT_MASK_SINITM                           0x0001
98
99#define TWI_FIFO_CTL_RCVINTLEN                        0x0008
100#define TWI_FIFO_CTL_XMTINTLEN                        0x0004
101#define TWI_FIFO_CTL_RCVFLUSH                         0x0002
102#define TWI_FIFO_CTL_XMTFLUSH                         0x0001
103
104#define TWI_FIFO_STAT_RCVSTAT_MASK                    0x000c
105#define TWI_FIFO_STAT_RCVSTAT_EMPTY                   0x0000
106#define TWI_FIFO_STAT_RCVSTAT_SHIFT                        2
107#define TWI_FIFO_STAT_XMTSTAT_MASK                    0x0003
108#define TWI_FIFO_STAT_XMTSTAT_FULL                    0x0003
109#define TWI_FIFO_STAT_XMTSTAT_SHIFT                        0
110
111#define TWI_XMT_DATA8_XMTDATA8_MASK                   0x00ff
112#define TWI_XMT_DATA8_XMTDATA8_SHIFT                       0
113
114#define TWI_RCV_DATA8_RCVDATA8_MASK                   0x00ff
115#define TWI_RCV_DATA8_RCVDATA8_SHIFT                       0
116
117
118#endif /* _twiRegs_h_ */
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