source: rtems/bsps/bfin/include/libcpu/spiRegs.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*  Blackfin SPI Registers
2 *
3 *  Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA
4 *             written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _spiRegs_h_
12#define _spiRegs_h_
13
14
15/* register addresses */
16
17#define SPI_CTL_OFFSET                                0x0000
18#define SPI_FLG_OFFSET                                0x0004
19#define SPI_STAT_OFFSET                               0x0008
20#define SPI_TDBR_OFFSET                               0x000c
21#define SPI_RDBR_OFFSET                               0x0010
22#define SPI_BAUD_OFFSET                               0x0014
23#define SPI_SHADOW_OFFSET                             0x0018
24
25
26/* register fields */
27
28#define SPI_CTL_SPE                                   0x4000
29#define SPI_CTL_WOM                                   0x2000
30#define SPI_CTL_MSTR                                  0x1000
31#define SPI_CTL_CPOL                                  0x0800
32#define SPI_CTL_CPHA                                  0x0400
33#define SPI_CTL_LSBF                                  0x0200
34#define SPI_CTL_SIZE                                  0x0100
35#define SPI_CTL_EMISO                                 0x0020
36#define SPI_CTL_PSSE                                  0x0010
37#define SPI_CTL_GM                                    0x0008
38#define SPI_CTL_SZ                                    0x0004
39#define SPI_CTL_TIMOD_MASK                            0x0003
40#define SPI_CTL_TIMOD_RDBR                            0x0000
41#define SPI_CTL_TIMOD_TDBR                            0x0001
42#define SPI_CTL_TIMOD_DMA_RDBR                        0x0002
43#define SPI_CTL_TIMOD_DMA_TDBR                        0x0003
44
45#define SPI_FLG_FLG7                                  0x8000
46#define SPI_FLG_FLG6                                  0x4000
47#define SPI_FLG_FLG5                                  0x2000
48#define SPI_FLG_FLG4                                  0x1000
49#define SPI_FLG_FLG3                                  0x0800
50#define SPI_FLG_FLG2                                  0x0400
51#define SPI_FLG_FLG1                                  0x0200
52#define SPI_FLG_FLS7                                  0x0080
53#define SPI_FLG_FLS6                                  0x0040
54#define SPI_FLG_FLS5                                  0x0020
55#define SPI_FLG_FLS4                                  0x0010
56#define SPI_FLG_FLS3                                  0x0008
57#define SPI_FLG_FLS2                                  0x0004
58#define SPI_FLG_FLS1                                  0x0002
59
60#define SPI_STAT_TXCOL                                0x0040
61#define SPI_STAT_RXS                                  0x0020
62#define SPI_STAT_RBSY                                 0x0010
63#define SPI_STAT_TXS                                  0x0008
64#define SPI_STAT_TXE                                  0x0004
65#define SPI_STAT_MODF                                 0x0002
66#define SPI_STAT_SPIF                                 0x0001
67
68
69#endif /* _spiRegs_h_ */
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