source: rtems/bsps/bfin/include/libcpu/bf533.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 6.6 KB
Line 
1/*  Blackfin BF533 Definitions
2 *
3 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 *             written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _bf533_h_
12#define _bf533_h_
13
14/* register (or register block) addresses */
15
16#define SIC_BASE_ADDRESS                          0xffc00100
17#define WDOG_BASE_ADDRESS                         0xffc00200
18#define RTC_BASE_ADDRESS                          0xffc00300
19#define UART0_BASE_ADDRESS                        0xffc00400
20#define SPI_BASE_ADDRESS                          0xffc00500
21#define TIMER_BASE_ADDRESS                        0xffc00600
22#define TIMER_CHANNELS                                     3
23#define TIMER_PITCH                                     0x10
24#define TIMER0_BASE_ADDRESS                       0xffc00600
25#define TIMER1_BASE_ADDRESS                       0xffc00610
26#define TIMER2_BASE_ADDRESS                       0xffc00620
27#define TIMER_ENABLE                              0xffc00640
28#define TIMER_DISABLE                             0xffc00644
29#define TIMER_STATUS                              0xffc00648
30#define PORTFIO_BASE_ADDRESS                      0xffc00700
31#define SPORT0_BASE_ADDRESS                       0xffc00800
32#define SPORT1_BASE_ADDRESS                       0xffc00900
33#define EBIU_BASE_ADDRESS                         0xffc00a00
34#define DMA_TC_PER                                0xffc00b0c
35#define DMA_TC_CNT                                0xffc00b10
36#define DMA_BASE_ADDRESS                          0xffc00c00
37#define DMA_CHANNELS                                       8
38#define DMA_PITCH                                       0x40
39#define DMA0_BASE_ADDRESS                         0xffc00c00
40#define DMA1_BASE_ADDRESS                         0xffc00c40
41#define DMA2_BASE_ADDRESS                         0xffc00c80
42#define DMA3_BASE_ADDRESS                         0xffc00cc0
43#define DMA4_BASE_ADDRESS                         0xffc00d00
44#define DMA5_BASE_ADDRESS                         0xffc00d40
45#define DMA6_BASE_ADDRESS                         0xffc00d80
46#define DMA7_BASE_ADDRESS                         0xffc00dc0
47#define MDMA_BASE_ADDRESS                         0xffc00e00
48#define MDMA_CHANNELS                                      2
49#define MDMA_D_S                                        0x40
50#define MDMA_PITCH                                      0x80
51#define MDMA0D_BASE_ADDRESS                       0xffc00e00
52#define MDMA0S_BASE_ADDRESS                       0xffc00e40
53#define MDMA1D_BASE_ADDRESS                       0xffc00e80
54#define MDMA1S_BASE_ADDRESS                       0xffc00ec0
55#define PPI_BASE_ADDRESS                          0xffc01000
56
57
58/* register fields */
59
60#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
61#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
62#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
63#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
64#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
65#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
66#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
67#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
68
69#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
70#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
71#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
72#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
73#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
74#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
75#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
76#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
77
78#define TIMER_ENABLE_TIMEN2                           0x0004
79#define TIMER_ENABLE_TIMEN1                           0x0002
80#define TIMER_ENABLE_TIMEN0                           0x0001
81
82#define TIMER_DISABLE_TIMDIS2                         0x0004
83#define TIMER_DISABLE_TIMDIS1                         0x0002
84#define TIMER_DISABLE_TIMDIS0                         0x0001
85
86#define TIMER_STATUS_TRUN2                        0x00004000
87#define TIMER_STATUS_TRUN1                        0x00002000
88#define TIMER_STATUS_TRUN0                        0x00001000
89#define TIMER_STATUS_TOVF_ERR2                    0x00000040
90#define TIMER_STATUS_TOVF_ERR1                    0x00000020
91#define TIMER_STATUS_TOVF_ERR0                    0x00000010
92#define TIMER_STATUS_TIMIL2                       0x00000004
93#define TIMER_STATUS_TIMIL1                       0x00000002
94#define TIMER_STATUS_TIMIL0                       0x00000001
95
96/* Core Event Controller vectors */
97
98#define CEC_EMULATION_VECTOR                               0
99#define CEC_RESET_VECTOR                                   1
100#define CEC_NMI_VECTOR                                     2
101#define CEC_EXCEPTIONS_VECTOR                              3
102#define CEC_HARDWARE_ERROR_VECTOR                          5
103#define CEC_CORE_TIMER_VECTOR                              6
104#define CEC_INTERRUPT_BASE_VECTOR                          7
105#define CEC_INTERRUPT_COUNT                                9
106
107
108/* System Interrupt Controller vectors */
109
110#define SIC_IAR_COUNT                                      3
111
112#define SIC_PLL_WAKEUP_VECTOR                              0
113#define SIC_DMA_ERROR_VECTOR                               1
114#define SIC_PPI_ERROR_VECTOR                               2
115#define SIC_SPORT0_ERROR_VECTOR                            3
116#define SIC_SPORT1_ERROR_VECTOR                            4
117#define SIC_SPI_ERROR_VECTOR                               5
118#define SIC_UART0_ERROR_VECTOR                             6
119#define SIC_RTC_VECTOR                                     7
120#define SIC_DMA0_PPI_VECTOR                                8
121#define SIC_DMA1_SPORT0_RX_VECTOR                          9
122#define SIC_DMA2_SPORT0_TX_VECTOR                         10
123#define SIC_DMA3_SPORT1_RX_VECTOR                         11
124#define SIC_DMA4_SPORT1_TX_VECTOR                         12
125#define SIC_DMA5_SPI_VECTOR                               13
126#define SIC_DMA6_UART0_RX_VECTOR                          14
127#define SIC_DMA7_UART0_TX_VECTOR                          15
128#define SIC_TIMER0_VECTOR                                 16
129#define SIC_TIMER1_VECTOR                                 17
130#define SIC_TIMER2_VECTOR                                 18
131#define SIC_MDMA0_VECTOR                                  21
132#define SIC_MDMA1_VECTOR                                  22
133#define SIC_WATCHDOG_VECTOR                               23
134
135#endif /* _bf533_h_ */
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