source: rtems/bsps/bfin/include/bf52x.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/**
2 *@file bf52x.h
3 *
4 *@brief
5 *  - This file provides the register address for the 52X model. The file is
6 *  based on the 533 implementation with some addition to support 52X range of
7 *  processors.
8 *
9 * Target:   TLL6527v1-0
10 * Compiler:
11 *
12 * COPYRIGHT (c) 2010 by ECE Northeastern University.
13 *
14 * The license and distribution terms for this file may be
15 * found in the file LICENSE in this distribution or at
16 * http://www.rtems.org/license
17 *
18 * @author Rohan Kangralkar, ECE, Northeastern University
19 *         (kangralkar.r@husky.neu.edu)
20 *
21 * LastChange:
22 */
23
24#ifndef _BF52X_H_
25#define _BF52X_H_
26
27/* register (or register block) addresses */
28
29#define SIC_BASE_ADDRESS                          0xffc00100
30#define WDOG_BASE_ADDRESS                         0xffc00200
31#define RTC_BASE_ADDRESS                          0xffc00300
32#define UART0_BASE_ADDRESS                        0xffc00400
33#define UART1_BASE_ADDRESS                        0xffc02000
34#define SPI_BASE_ADDRESS                          0xffc00500
35#define TIMER_BASE_ADDRESS                        0xffc00600
36#define TIMER_CHANNELS                                     3
37#define TIMER_PITCH                                     0x10
38#define TIMER0_BASE_ADDRESS                       0xffc00600
39#define TIMER1_BASE_ADDRESS                       0xffc00610
40#define TIMER2_BASE_ADDRESS                       0xffc00620
41#define TIMER_ENABLE                              0xffc00640
42#define TIMER_DISABLE                             0xffc00644
43#define TIMER_STATUS                              0xffc00648
44#define PORTFIO_BASE_ADDRESS                      0xffc00700
45#define SPORT0_BASE_ADDRESS                       0xffc00800
46#define SPORT1_BASE_ADDRESS                       0xffc00900
47#define EBIU_BASE_ADDRESS                         0xffc00a00
48#define DMA_TC_PER                                0xffc00b0c
49#define DMA_TC_CNT                                0xffc00b10
50#define DMA_BASE_ADDRESS                          0xffc00c00
51#define DMA_CHANNELS                                       8
52#define DMA_PITCH                                       0x40
53#define DMA0_BASE_ADDRESS                         0xffc00c00
54#define DMA1_BASE_ADDRESS                         0xffc00c40
55#define DMA2_BASE_ADDRESS                         0xffc00c80
56#define DMA3_BASE_ADDRESS                         0xffc00cc0
57#define DMA4_BASE_ADDRESS                         0xffc00d00
58#define DMA5_BASE_ADDRESS                         0xffc00d40
59#define DMA6_BASE_ADDRESS                         0xffc00d80
60#define DMA7_BASE_ADDRESS                         0xffc00dc0
61#define DMA8_BASE_ADDRESS                         0xffc00e00
62#define DMA9_BASE_ADDRESS                         0xffc00e40
63#define DMA10_BASE_ADDRESS                        0xffc00e80
64#define DMA11_BASE_ADDRESS                        0xffc00ec0
65#define MDMA_BASE_ADDRESS                         0xffc00e00
66#define MDMA_CHANNELS                                      2
67#define MDMA_D_S                                        0x40
68#define MDMA_PITCH                                      0x80
69#define MDMA0D_BASE_ADDRESS                       0xffc00e00
70#define MDMA0S_BASE_ADDRESS                       0xffc00e40
71#define MDMA1D_BASE_ADDRESS                       0xffc00e80
72#define MDMA1S_BASE_ADDRESS                       0xffc00ec0
73#define PPI_BASE_ADDRESS                          0xffc01000
74
75
76/* register fields */
77
78#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
79#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
80#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
81#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
82#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
83#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
84#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
85#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
86
87#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
88#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
89#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
90#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
91#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
92#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
93#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
94#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
95
96#define TIMER_ENABLE_TIMEN2                           0x0004
97#define TIMER_ENABLE_TIMEN1                           0x0002
98#define TIMER_ENABLE_TIMEN0                           0x0001
99
100#define TIMER_DISABLE_TIMDIS2                         0x0004
101#define TIMER_DISABLE_TIMDIS1                         0x0002
102#define TIMER_DISABLE_TIMDIS0                         0x0001
103
104#define TIMER_STATUS_TRUN2                        0x00004000
105#define TIMER_STATUS_TRUN1                        0x00002000
106#define TIMER_STATUS_TRUN0                        0x00001000
107#define TIMER_STATUS_TOVF_ERR2                    0x00000040
108#define TIMER_STATUS_TOVF_ERR1                    0x00000020
109#define TIMER_STATUS_TOVF_ERR0                    0x00000010
110#define TIMER_STATUS_TIMIL2                       0x00000004
111#define TIMER_STATUS_TIMIL1                       0x00000002
112#define TIMER_STATUS_TIMIL0                       0x00000001
113
114/* Core Event Controller vectors */
115
116#define CEC_EMULATION_VECTOR                               0
117#define CEC_RESET_VECTOR                                   1
118#define CEC_NMI_VECTOR                                     2
119#define CEC_EXCEPTIONS_VECTOR                              3
120#define CEC_HARDWARE_ERROR_VECTOR                          5
121#define CEC_CORE_TIMER_VECTOR                              6
122#define CEC_INTERRUPT_BASE_VECTOR                          7
123#define CEC_INTERRUPT_COUNT                                9
124
125
126/* System Interrupt Controller vectors */
127
128#define SIC_IAR_COUNT                                      8
129
130#endif /* _BF52X_H_ */
131
Note: See TracBrowser for help on using the repository browser.