[cb4c90b2] | 1 | /** |
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| 2 | *@file interrupt.c |
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| 3 | * |
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| 4 | *@brief |
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| 5 | * - This file implements interrupt dispatcher. Most of the code is taken from |
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| 6 | * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR |
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| 7 | * registers some portion is written twice. |
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| 8 | * |
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| 9 | * Target: TLL6527v1-0 |
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| 10 | * Compiler: |
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| 11 | * |
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| 12 | * COPYRIGHT (c) 2010 by ECE Northeastern University. |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license |
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[cb4c90b2] | 17 | * |
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| 18 | * @author Rohan Kangralkar, ECE, Northeastern University |
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| 19 | * (kangralkar.r@husky.neu.edu) |
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| 20 | * |
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| 21 | * LastChange: |
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| 22 | */ |
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| 23 | |
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| 24 | #include <rtems.h> |
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| 25 | #include <rtems/libio.h> |
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| 26 | |
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| 27 | #include <bsp.h> |
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| 28 | #include <libcpu/cecRegs.h> |
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| 29 | #include <libcpu/sicRegs.h> |
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[b2ed712] | 30 | #include <string.h> |
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[9dd2fdb9] | 31 | #include <bsp/interrupt.h> |
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[cb4c90b2] | 32 | |
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| 33 | #define SIC_IAR_COUNT_SET0 4 |
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| 34 | #define SIC_IAR_BASE_ADDRESS_0 0xFFC00150 |
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| 35 | |
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| 36 | /** |
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| 37 | * There are two implementations for the interrupt handler. |
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| 38 | * 1. INTERRUPT_USE_TABLE: uses tables for finding the right ISR. |
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| 39 | * 2. Uses link list to find the user ISR. |
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| 40 | * |
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| 41 | * |
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| 42 | * 1. INTERRUPT_USE_TABLE |
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| 43 | * Space requirement: |
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| 44 | * - Array to hold CEC masks size: CEC_INTERRUPT_COUNT(9)*(2*int).9*2*4= 72B |
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| 45 | * - Array to hold isr function pointers IRQ_MAX(56)*sizeof(bfin_isr_t)= 896B |
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| 46 | * - Array for bit twidlling 32 bytes. |
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| 47 | * - Global Mask 8 bytes. |
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| 48 | * - Total = 1008 Bytes Aprox |
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| 49 | * |
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| 50 | * Time requirements |
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| 51 | * The worst case time is about the same for jumping to the user ISR. With a |
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| 52 | * variance of one conditional statement. |
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| 53 | * |
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| 54 | * 2. Using link list. |
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| 55 | * Space requirement: |
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| 56 | * - Array to hold CEC mask CEC_INTERRUPT_COUNT(9)*(sizeof(vectors)). |
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| 57 | * 9*3*4= 108B |
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| 58 | * - Array to hold isr IRQ_MAX(56)*sizeof(bfin_isr_t) The structure has |
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| 59 | * additional pointers 56*7*4=1568B |
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| 60 | * - Global Mask 8 bytes. |
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| 61 | * Total = 1684. |
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| 62 | * Time requirements |
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| 63 | * In the worst case all the lines can be on one CEC line to 56 entries have |
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| 64 | * to be traversed to find the right user ISR. |
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| 65 | * But this implementation has benefit of being flexible, Providing |
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| 66 | * additional user assigned priority. and may consume less space |
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| 67 | * if all devices are not supported. |
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| 68 | */ |
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| 69 | |
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| 70 | /** |
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| 71 | * TODO: To place the dispatcher routine code in L1. |
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| 72 | */ |
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| 73 | |
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| 74 | #if INTERRUPT_USE_TABLE |
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| 75 | |
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| 76 | |
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| 77 | /****************************************************************************** |
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| 78 | * Static variables |
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| 79 | *****************************************************************************/ |
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| 80 | /** |
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| 81 | * @var sic_isr0_mask |
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| 82 | * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device |
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| 83 | * the relevant SIC_ISRx bit is not cleared unless the interrupt |
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| 84 | * service routine clears the mechanism that generated interrupt |
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| 85 | */ |
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| 86 | static uint32_t sic_isr0_mask = 0; |
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| 87 | |
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| 88 | /** |
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| 89 | * @var sic_isr0_mask |
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| 90 | * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device |
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| 91 | * the relevant SIC_ISRx bit is not cleared unless the interrupt |
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| 92 | * service routine clears the mechanism that generated interrupt |
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| 93 | */ |
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| 94 | static uint32_t sic_isr1_mask = 0; |
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| 95 | |
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| 96 | |
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| 97 | /** |
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| 98 | * @var sic_isr |
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| 99 | * @brief An array of sic register mask for each of the 16 core interrupt lines |
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| 100 | */ |
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| 101 | static struct { |
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| 102 | uint32_t mask0; |
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| 103 | uint32_t mask1; |
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| 104 | } vectors[CEC_INTERRUPT_COUNT]; |
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| 105 | |
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| 106 | /** |
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| 107 | * @var ivt |
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| 108 | * @brief Contains a table of ISR and arguments. The ISR jumps directly to |
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| 109 | * these ISR. |
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| 110 | */ |
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| 111 | static bfin_isr_t ivt[IRQ_MAX]; |
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| 112 | |
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| 113 | /** |
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| 114 | * http://graphics.stanford.edu/~seander/bithacks.html for more details |
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| 115 | */ |
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| 116 | static const char clz_table[32] = |
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| 117 | { |
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| 118 | 0, 31, 9, 30, 3, 8, 18, 29, 2, 5, 7, 14, 12, 17, |
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| 119 | 22, 28, 1, 10, 4, 19, 6, 15, 13, 23, 11, 20, 16, |
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| 120 | 24, 21, 25, 26, 27 |
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| 121 | }; |
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| 122 | |
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| 123 | /** |
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| 124 | * finds the first bit set from the left. look at |
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| 125 | * http://graphics.stanford.edu/~seander/bithacks.html for more details |
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| 126 | * @param n |
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| 127 | * @return |
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| 128 | */ |
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| 129 | static unsigned long clz(unsigned long n) |
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| 130 | { |
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| 131 | unsigned long c = 0x7dcd629; /* magic constant... */ |
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| 132 | |
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| 133 | n |= (n >> 1); |
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| 134 | n |= (n >> 2); |
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| 135 | n |= (n >> 4); |
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| 136 | n |= (n >> 8); |
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| 137 | n |= (n >> 16); |
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| 138 | if (n == 0) return 32; |
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| 139 | n = c + (c * n); |
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| 140 | return 31 - clz_table[n >> 27]; /* For little endian */ |
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| 141 | } |
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| 142 | |
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| 143 | |
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| 144 | |
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| 145 | /** |
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| 146 | * Centralized Interrupt dispatcher routine. This routine dispatches interrupts |
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| 147 | * to the user ISR. The priority is according to the blackfin SIC. |
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| 148 | * The first level of priority is handled in the hardware at the core event |
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| 149 | * controller. The second level of interrupt is handled according to the line |
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| 150 | * number that goes in to the SIC. |
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| 151 | * * SIC_0 has higher priority than SIC 1. |
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| 152 | * * Inside the SIC the priority is assigned according to the line number. |
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| 153 | * Lower the line number higher the priority. |
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| 154 | * |
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| 155 | * In order to change the interrupt priority we may |
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| 156 | * 1. change the SIC IAR registers or |
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| 157 | * 2. Assign priority and extract it inside this function and call the ISR |
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| 158 | * according tot the priority. |
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| 159 | * |
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| 160 | * @param vector IVG number. |
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| 161 | * @return |
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| 162 | */ |
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| 163 | static rtems_isr interruptHandler(rtems_vector_number vector) { |
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| 164 | uint32_t mask = 0; |
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| 165 | int id = 0; |
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| 166 | /** |
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| 167 | * Enable for debugging |
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| 168 | * |
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| 169 | * static volatile uint32_t spurious_sic0 = 0; |
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| 170 | * static volatile uint32_t spurious_source = 0; |
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| 171 | * static volatile uint32_t spurious_sic1 = 0; |
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| 172 | */ |
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| 173 | |
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| 174 | /** |
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| 175 | * Extract the vector number relative to the SIC start line |
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| 176 | */ |
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| 177 | vector -= CEC_INTERRUPT_BASE_VECTOR; |
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| 178 | |
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| 179 | /** |
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| 180 | * Check for bounds |
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| 181 | */ |
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| 182 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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| 183 | |
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| 184 | /** |
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| 185 | * Extract information and execute ISR from SIC 0 |
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| 186 | */ |
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| 187 | mask = *(uint32_t volatile *) SIC_ISR & |
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| 188 | *(uint32_t volatile *) SIC_IMASK & vectors[vector].mask0; |
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| 189 | id = clz(mask); |
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| 190 | if ( SIC_ISR0_MAX > id ) { |
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| 191 | /** Parameter check */ |
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| 192 | if( NULL != ivt[id].pFunc) { |
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| 193 | /** Call the relevant function with argument */ |
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| 194 | ivt[id].pFunc( ivt[id].pArg ); |
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| 195 | } else { |
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| 196 | /** |
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| 197 | * spurious interrupt we should not be getting this |
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| 198 | * spurious_sic0++; |
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| 199 | * spurious_source = id; |
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| 200 | */ |
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| 201 | } |
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| 202 | } else { |
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| 203 | /** |
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| 204 | * we look at SIC 1 |
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| 205 | */ |
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| 206 | } |
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| 207 | |
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| 208 | |
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| 209 | /** |
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| 210 | * Extract information and execute ISR from SIC 1 |
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| 211 | */ |
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| 212 | mask = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & |
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| 213 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) & |
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| 214 | vectors[vector].mask1; |
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| 215 | id = clz(mask)+SIC_ISR0_MAX; |
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| 216 | if ( IRQ_MAX > id ) { |
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| 217 | /** Parameter Check */ |
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| 218 | if( NULL != ivt[id].pFunc ) { |
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| 219 | /** Call the relevant function with argument */ |
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| 220 | ivt[id].pFunc( ivt[id].pArg ); |
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| 221 | } else { |
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| 222 | /** |
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| 223 | * spurious interrupt we should not be getting this |
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| 224 | * |
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| 225 | * spurious_sic1++; |
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| 226 | * spurious_source = id; |
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| 227 | */ |
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| 228 | } |
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| 229 | } else { |
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| 230 | /** |
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| 231 | * we continue |
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| 232 | */ |
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| 233 | } |
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| 234 | |
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| 235 | } |
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| 236 | } |
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| 237 | |
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| 238 | |
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| 239 | |
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| 240 | /** |
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| 241 | * This routine registers a new ISR. It will write a new entry to the IVT table |
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| 242 | * @param isr contains a callback function and source |
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| 243 | * @return rtems status code |
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| 244 | */ |
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| 245 | rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) { |
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| 246 | rtems_interrupt_level isrLevel; |
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| 247 | int id = 0; |
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| 248 | int position = 0; |
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| 249 | |
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| 250 | /** |
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| 251 | * Sanity Check |
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| 252 | */ |
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| 253 | if ( NULL == isr ){ |
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| 254 | return RTEMS_UNSATISFIED; |
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| 255 | } |
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| 256 | |
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| 257 | /** |
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| 258 | * Sanity check. The register function should at least provide callback func |
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| 259 | */ |
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| 260 | if ( NULL == isr->pFunc ) { |
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| 261 | return RTEMS_UNSATISFIED; |
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| 262 | } |
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| 263 | |
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| 264 | id = isr->source; |
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| 265 | |
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| 266 | /** |
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| 267 | * Parameter Check. We already have a function registered here. First |
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| 268 | * unregister and then a new function can be allocated. |
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| 269 | */ |
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| 270 | if ( NULL != ivt[id].pFunc ) { |
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| 271 | return RTEMS_UNSATISFIED; |
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| 272 | } |
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| 273 | |
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| 274 | rtems_interrupt_disable(isrLevel); |
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| 275 | /** |
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| 276 | * Assign the new function pointer to the ISR Dispatcher |
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| 277 | * */ |
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| 278 | ivt[id].pFunc = isr->pFunc; |
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| 279 | ivt[id].pArg = isr->pArg; |
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| 280 | |
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| 281 | |
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| 282 | /** find out which isr mask has to be set to enable the interrupt */ |
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| 283 | if ( SIC_ISR0_MAX > id ) { |
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| 284 | sic_isr0_mask |= 0x1<<id; |
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| 285 | *(uint32_t volatile *) SIC_IMASK |= 0x1<<id; |
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| 286 | } else { |
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| 287 | position = id - SIC_ISR0_MAX; |
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| 288 | sic_isr1_mask |= 0x1<<position; |
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| 289 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= 0x1<<position; |
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| 290 | } |
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| 291 | |
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| 292 | rtems_interrupt_enable(isrLevel); |
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| 293 | |
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| 294 | return RTEMS_SUCCESSFUL; |
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| 295 | } |
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| 296 | |
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| 297 | |
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| 298 | /** |
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| 299 | * This function unregisters a registered interrupt handler. |
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| 300 | * @param isr |
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| 301 | */ |
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| 302 | rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) { |
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| 303 | rtems_interrupt_level isrLevel; |
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| 304 | int id = 0; |
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| 305 | int position = 0; |
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| 306 | |
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| 307 | /** |
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| 308 | * Sanity Check |
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| 309 | */ |
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| 310 | if ( NULL == isr ){ |
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| 311 | return RTEMS_UNSATISFIED; |
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| 312 | } |
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| 313 | |
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| 314 | id = isr->source; |
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| 315 | |
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| 316 | rtems_interrupt_disable(isrLevel); |
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| 317 | /** |
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| 318 | * Assign the new function pointer to the ISR Dispatcher |
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| 319 | * */ |
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| 320 | ivt[id].pFunc = NULL; |
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| 321 | ivt[id].pArg = NULL; |
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| 322 | |
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| 323 | |
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| 324 | /** find out which isr mask has to be set to enable the interrupt */ |
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| 325 | if ( SIC_ISR0_MAX > id ) { |
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| 326 | sic_isr0_mask &= ~(0x1<<id); |
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| 327 | *(uint32_t volatile *) SIC_IMASK &= ~(0x1<<id); |
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| 328 | } else { |
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| 329 | position = id - SIC_ISR0_MAX; |
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| 330 | sic_isr1_mask &= ~(0x1<<position); |
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| 331 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) &= ~(0x1<<position); |
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| 332 | } |
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| 333 | |
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| 334 | rtems_interrupt_enable(isrLevel); |
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| 335 | |
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| 336 | return RTEMS_SUCCESSFUL; |
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| 337 | } |
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| 338 | |
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| 339 | |
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| 340 | |
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| 341 | |
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| 342 | /** |
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| 343 | * blackfin interrupt initialization routine. It initializes the bfin ISR |
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| 344 | * dispatcher. It will also create SIC CEC map which will be used for |
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| 345 | * identifying the ISR. |
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| 346 | */ |
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| 347 | void bfin_interrupt_init(void) { |
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| 348 | int source; |
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| 349 | int vector; |
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| 350 | uint32_t r; |
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| 351 | int i; |
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| 352 | int j; |
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| 353 | |
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| 354 | *(uint32_t volatile *) SIC_IMASK = 0; |
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| 355 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0; |
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| 356 | |
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| 357 | memset(vectors, 0, sizeof(vectors)); |
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| 358 | /* build mask0 showing what SIC sources drive each CEC vector */ |
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| 359 | source = 0; |
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| 360 | |
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| 361 | /** |
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| 362 | * The bf52x has 8 IAR registers but they do not have a constant pitch. |
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| 363 | * |
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| 364 | */ |
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| 365 | for (i = 0; i < SIC_IAR_COUNT; i++) { |
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| 366 | if ( SIC_IAR_COUNT_SET0 > i ) { |
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| 367 | r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); |
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| 368 | } else { |
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| 369 | r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 + |
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| 370 | ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH)); |
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| 371 | } |
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| 372 | |
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| 373 | for (j = 0; j < 8; j++) { |
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| 374 | vector = r & 0x0f; |
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| 375 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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| 376 | /* install our local handler */ |
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| 377 | if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){ |
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| 378 | set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); |
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| 379 | } |
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| 380 | if ( SIC_ISR0_MAX > source ) { |
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| 381 | vectors[vector].mask0 |= (1 << source); |
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| 382 | } else { |
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| 383 | vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX)); |
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| 384 | } |
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| 385 | } |
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| 386 | r >>= 4; |
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| 387 | source++; |
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| 388 | } |
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| 389 | } |
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| 390 | } |
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| 391 | |
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| 392 | |
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| 393 | |
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| 394 | |
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| 395 | |
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| 396 | #else |
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| 397 | |
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| 398 | static struct { |
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| 399 | uint32_t mask0; |
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| 400 | uint32_t mask1; |
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| 401 | bfin_isr_t *head; |
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| 402 | } vectors[CEC_INTERRUPT_COUNT]; |
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| 403 | |
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| 404 | static uint32_t globalMask0; |
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| 405 | static uint32_t globalMask1; |
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| 406 | |
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| 407 | static rtems_isr interruptHandler(rtems_vector_number vector) { |
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| 408 | bfin_isr_t *isr = NULL; |
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| 409 | uint32_t sourceMask0 = 0; |
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| 410 | uint32_t sourceMask1 = 0; |
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| 411 | rtems_interrupt_level isrLevel; |
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| 412 | |
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| 413 | rtems_interrupt_disable(isrLevel); |
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| 414 | vector -= CEC_INTERRUPT_BASE_VECTOR; |
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| 415 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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| 416 | isr = vectors[vector].head; |
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| 417 | sourceMask0 = *(uint32_t volatile *) SIC_ISR & |
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| 418 | *(uint32_t volatile *) SIC_IMASK; |
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| 419 | sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & |
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| 420 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH); |
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| 421 | while (isr) { |
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| 422 | if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) { |
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| 423 | isr->isr(isr->_arg); |
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| 424 | sourceMask0 = *(uint32_t volatile *) SIC_ISR & |
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| 425 | *(uint32_t volatile *) SIC_IMASK; |
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| 426 | sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & |
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| 427 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH); |
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| 428 | } |
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| 429 | isr = isr->next; |
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| 430 | } |
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| 431 | } |
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| 432 | rtems_interrupt_enable(isrLevel); |
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| 433 | } |
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| 434 | |
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| 435 | /** |
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| 436 | * Initializes the interrupt module |
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| 437 | */ |
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| 438 | void bfin_interrupt_init(void) { |
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| 439 | int source; |
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| 440 | int vector; |
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| 441 | uint32_t r; |
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| 442 | int i; |
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| 443 | int j; |
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| 444 | |
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| 445 | globalMask0 = ~(uint32_t) 0; |
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| 446 | globalMask1 = ~(uint32_t) 0; |
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| 447 | *(uint32_t volatile *) SIC_IMASK = 0; |
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| 448 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0; |
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| 449 | |
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| 450 | memset(vectors, 0, sizeof(vectors)); |
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| 451 | /* build mask0 showing what SIC sources drive each CEC vector */ |
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| 452 | source = 0; |
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| 453 | |
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| 454 | /** |
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| 455 | * The bf52x has 8 IAR registers but they do not have a constant pitch. |
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| 456 | * |
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| 457 | */ |
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| 458 | for (i = 0; i < SIC_IAR_COUNT; i++) { |
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| 459 | if ( SIC_IAR_COUNT_SET0 > i ) { |
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| 460 | r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); |
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| 461 | } else { |
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| 462 | r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 + |
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| 463 | ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH)); |
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| 464 | } |
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| 465 | for (j = 0; j < 8; j++) { |
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| 466 | vector = r & 0x0f; |
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| 467 | if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { |
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| 468 | /* install our local handler */ |
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| 469 | if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){ |
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| 470 | set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); |
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| 471 | } |
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| 472 | if ( SIC_ISR0_MAX > source ) { |
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| 473 | vectors[vector].mask0 |= (1 << source); |
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| 474 | } else { |
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| 475 | vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX)); |
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| 476 | } |
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| 477 | } |
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| 478 | r >>= 4; |
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| 479 | source++; |
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| 480 | } |
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| 481 | } |
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| 482 | } |
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| 483 | |
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| 484 | /* modify SIC_IMASK based on ISR list for a particular CEC vector */ |
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| 485 | static void setMask(uint32_t vector) { |
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| 486 | bfin_isr_t *isr = NULL; |
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| 487 | uint32_t mask = 0; |
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| 488 | uint32_t r = 0; |
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| 489 | |
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| 490 | mask = 0; |
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| 491 | isr = vectors[vector].head; |
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| 492 | while (isr) { |
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| 493 | mask |= isr->mask0; |
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| 494 | isr = isr->next; |
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| 495 | } |
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| 496 | r = *(uint32_t volatile *) SIC_IMASK; |
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| 497 | r &= ~vectors[vector].mask0; |
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| 498 | r |= mask; |
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| 499 | r &= globalMask0; |
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| 500 | *(uint32_t volatile *) SIC_IMASK = r; |
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| 501 | |
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| 502 | |
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| 503 | mask = 0; |
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| 504 | isr = vectors[vector].head; |
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| 505 | while (isr) { |
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| 506 | mask |= isr->mask1; |
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| 507 | isr = isr->next; |
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| 508 | } |
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| 509 | r = *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH); |
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| 510 | r &= ~vectors[vector].mask1; |
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| 511 | r |= mask; |
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| 512 | r &= globalMask1; |
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| 513 | *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH) = r; |
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| 514 | } |
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| 515 | |
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| 516 | /* add an ISR to the list for whichever vector it belongs to */ |
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| 517 | rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) { |
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| 518 | bfin_isr_t *walk; |
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| 519 | rtems_interrupt_level isrLevel; |
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| 520 | |
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| 521 | /* find the appropriate vector */ |
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| 522 | for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++) |
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| 523 | if ( (vectors[isr->vector].mask0 & (1 << isr->source) ) || \ |
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| 524 | (vectors[isr->vector].mask1 & (1 << (isr->source - SIC_ISR0_MAX)) )) |
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| 525 | break; |
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| 526 | if (isr->vector < CEC_INTERRUPT_COUNT) { |
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| 527 | isr->next = NULL; |
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| 528 | isr->mask0 = 0; |
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| 529 | isr->mask1 = 0; |
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| 530 | rtems_interrupt_disable(isrLevel); |
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| 531 | /* find the current end of the list */ |
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| 532 | walk = vectors[isr->vector].head; |
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| 533 | while (walk && walk->next) |
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| 534 | walk = walk->next; |
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| 535 | /* append new isr to list */ |
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| 536 | if (walk) |
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| 537 | walk->next = isr; |
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| 538 | else |
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| 539 | vectors[isr->vector].head = isr; |
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| 540 | rtems_interrupt_enable(isrLevel); |
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| 541 | } else |
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| 542 | /* we failed, but make vector a legal value so other calls into |
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| 543 | this module with this isr descriptor won't do anything bad */ |
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| 544 | isr->vector = 0; |
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| 545 | return RTEMS_SUCCESSFUL; |
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| 546 | } |
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| 547 | |
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| 548 | rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) { |
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| 549 | bfin_isr_t *walk, *prev; |
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| 550 | rtems_interrupt_level isrLevel; |
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| 551 | |
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| 552 | rtems_interrupt_disable(isrLevel); |
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| 553 | walk = vectors[isr->vector].head; |
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| 554 | prev = NULL; |
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| 555 | /* find this isr in our list */ |
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| 556 | while (walk && walk != isr) { |
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| 557 | prev = walk; |
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| 558 | walk = walk->next; |
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| 559 | } |
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| 560 | if (walk) { |
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| 561 | /* if found, remove it */ |
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| 562 | if (prev) |
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| 563 | prev->next = walk->next; |
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| 564 | else |
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| 565 | vectors[isr->vector].head = walk->next; |
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| 566 | /* fix up SIC_IMASK if necessary */ |
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| 567 | setMask(isr->vector); |
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| 568 | } |
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| 569 | rtems_interrupt_enable(isrLevel); |
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| 570 | return RTEMS_SUCCESSFUL; |
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| 571 | } |
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| 572 | |
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| 573 | void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) { |
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| 574 | rtems_interrupt_level isrLevel; |
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| 575 | |
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| 576 | rtems_interrupt_disable(isrLevel); |
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| 577 | if ( SIC_ISR0_MAX > isr->source ) { |
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| 578 | isr->mask0 = enable ? (1 << isr->source) : 0; |
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| 579 | *(uint32_t volatile *) SIC_IMASK |= isr->mask0; |
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| 580 | } else { |
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| 581 | isr->mask1 = enable ? (1 << (isr->source - SIC_ISR0_MAX)) : 0; |
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| 582 | *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= isr->mask1; |
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| 583 | } |
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| 584 | |
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| 585 | //setMask(isr->vector); |
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| 586 | rtems_interrupt_enable(isrLevel); |
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| 587 | } |
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| 588 | |
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| 589 | void bfin_interrupt_enable_all(int source, bool enable) { |
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| 590 | rtems_interrupt_level isrLevel; |
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| 591 | int vector; |
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| 592 | bfin_isr_t *walk; |
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| 593 | |
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| 594 | for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) |
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| 595 | if ( (vectors[vector].mask0 & (1 << source) ) || \ |
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| 596 | (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) )) |
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| 597 | break; |
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| 598 | if (vector < CEC_INTERRUPT_COUNT) { |
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| 599 | rtems_interrupt_disable(isrLevel); |
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| 600 | walk = vectors[vector].head; |
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| 601 | while (walk) { |
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| 602 | walk->mask0 = enable ? (1 << source) : 0; |
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| 603 | walk = walk->next; |
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| 604 | } |
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| 605 | |
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| 606 | walk = vectors[vector].head; |
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| 607 | while (walk) { |
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| 608 | walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0; |
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| 609 | walk = walk->next; |
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| 610 | } |
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| 611 | setMask(vector); |
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| 612 | rtems_interrupt_enable(isrLevel); |
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| 613 | } |
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| 614 | } |
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| 615 | |
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| 616 | void bfin_interrupt_enable_global(int source, bool enable) { |
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| 617 | int vector; |
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| 618 | rtems_interrupt_level isrLevel; |
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| 619 | |
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| 620 | for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) |
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| 621 | if ( (vectors[vector].mask0 & (1 << source) ) || \ |
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| 622 | (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) )) |
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| 623 | break; |
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| 624 | if (vector < CEC_INTERRUPT_COUNT) { |
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| 625 | rtems_interrupt_disable(isrLevel); |
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| 626 | if ( SIC_ISR0_MAX > source ) { |
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| 627 | if (enable) |
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| 628 | globalMask0 |= 1 << source; |
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| 629 | else |
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| 630 | globalMask0 &= ~(1 << source); |
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| 631 | }else { |
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| 632 | if (enable) |
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| 633 | globalMask1 |= 1 << (source - SIC_ISR0_MAX); |
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| 634 | else |
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| 635 | globalMask1 &= ~(1 << (source - SIC_ISR0_MAX)); |
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| 636 | } |
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| 637 | setMask(vector); |
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| 638 | rtems_interrupt_enable(isrLevel); |
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| 639 | } |
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| 640 | } |
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| 641 | |
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| 642 | #endif |
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