1 | /* |
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2 | * SPDX-License-Identifier: BSD-2-Clause |
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3 | * |
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4 | * Copyright (C) 2013, 2014 embedded brains GmbH |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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25 | * POSSIBILITY OF SUCH DAMAGE. |
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26 | */ |
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27 | |
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28 | #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION |
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29 | |
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30 | #include <bsp.h> |
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31 | #include <bsp/start.h> |
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32 | #include <bsp/arm-cp15-start.h> |
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33 | #include <bsp/arm-a9mpcore-start.h> |
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34 | |
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35 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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36 | { |
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37 | uint32_t sctlr_val; |
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38 | |
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39 | sctlr_val = arm_cp15_get_control(); |
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40 | |
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41 | /* |
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42 | * Current U-boot loader seems to start kernel image |
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43 | * with I and D caches on and MMU enabled. |
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44 | * If RTEMS application image finds that cache is on |
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45 | * during startup then disable caches. |
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46 | */ |
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47 | if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) { |
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48 | if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) { |
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49 | /* |
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50 | * If the data cache is on then ensure that it is clean |
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51 | * before switching off to be extra carefull. |
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52 | */ |
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53 | arm_cp15_data_cache_clean_all_levels(); |
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54 | } |
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55 | arm_cp15_flush_prefetch_buffer(); |
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56 | sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A ); |
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57 | arm_cp15_set_control( sctlr_val ); |
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58 | } |
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59 | arm_cp15_instruction_cache_invalidate(); |
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60 | /* |
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61 | * The care should be taken there that no shared levels |
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62 | * are invalidated by secondary CPUs in SMP case. |
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63 | * It is not problem on Zynq because level of coherency |
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64 | * is L1 only and higher level is not maintained and seen |
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65 | * by CP15. So no special care to limit levels on the secondary |
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66 | * are required there. |
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67 | */ |
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68 | arm_cp15_data_cache_invalidate_all_levels(); |
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69 | arm_cp15_branch_predictor_invalidate_all(); |
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70 | arm_cp15_tlb_invalidate(); |
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71 | arm_cp15_flush_prefetch_buffer(); |
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72 | arm_a9mpcore_start_hook_0(); |
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73 | } |
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74 | |
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75 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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76 | { |
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77 | arm_a9mpcore_start_hook_1(); |
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78 | bsp_start_copy_sections(); |
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79 | zynq_setup_mmu_and_cache(); |
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80 | |
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81 | #if !defined(RTEMS_SMP) \ |
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82 | && (defined(BSP_DATA_CACHE_ENABLED) \ |
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83 | || defined(BSP_INSTRUCTION_CACHE_ENABLED)) |
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84 | /* Enable unified L2 cache */ |
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85 | rtems_cache_enable_data(); |
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86 | #endif |
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87 | |
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88 | bsp_start_clear_bss(); |
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89 | } |
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