source: rtems/bsps/arm/xilinx-zynq/start/bspreset.c

Last change on this file was 53d0924, checked in by Sebastian Huber <sebastian.huber@…>, on 03/19/24 at 08:55:35

dev/serial: Add Zynq UART kernel I/O support

Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.

  • Property mode set to 100644
File size: 1.9 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsARMZynq
7 *
8 * @brief This source file contains the implementation of bsp_reset().
9 */
10
11/*
12 * Copyright (C) 2013 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include <bsp.h>
37#include <bsp/bootcard.h>
38#include <dev/serial/zynq-uart-regs.h>
39
40void bsp_reset(void)
41{
42  volatile zynq_uart *regs =
43    (volatile zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR;
44  volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf8000008;
45  volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200;
46
47  zynq_uart_reset_tx_flush(regs);
48
49  while (true) {
50    *slcr_unlock = 0xdf0d;
51    *pss_rst_ctrl = 0x1;
52  }
53}
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