source: rtems/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h @ f1eedbd

5
Last change on this file since f1eedbd was f1eedbd, checked in by Sebastian Huber <sebastian.huber@…>, on 04/09/19 at 05:12:21

bsp/xilinx-zynq: Relicense to BSD-2-Clause

Relicense contributions from Chris Johns, Christian Mauderer,
embedded brains GmbH, Joel Sherrill, OAR, Pavel Pisa, Ralf Kirchner, and
Sebastian Huber.

Update #3053.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/**
2 * @file
3 * @ingroup zynq_uart_regs
4 * @brief UART register definitions.
5 */
6
7/*
8 * SPDX-License-Identifier: BSD-2-Clause
9 *
10 * Copyright (C) 2013 embedded brains GmbH
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/**
35 * @defgroup zynq_uart_regs UART Register Definitions
36 * @ingroup zynq_uart
37 * @brief UART Register Definitions
38 * @{
39 */
40
41#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
42#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
43
44#include <bsp/utility.h>
45
46#define ZYNQ_UART_FIFO_DEPTH 64
47
48typedef struct zynq_uart {
49        uint32_t control;
50#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
51#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
52#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
53#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
54#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
55#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
56#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
57#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
58#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
59        uint32_t mode;
60#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
61#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
62#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
63#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
64#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
65#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
66#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
67#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
68#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
69#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
70#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
71#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
72#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
73#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
74#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
75#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
76#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
77#define ZYNQ_UART_MODE_PAR_ODD 0x01U
78#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
79#define ZYNQ_UART_MODE_PAR_MARK 0x03U
80#define ZYNQ_UART_MODE_PAR_NONE 0x04U
81#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
82#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
83#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
84#define ZYNQ_UART_MODE_CHRL_8 0x00U
85#define ZYNQ_UART_MODE_CHRL_7 0x02U
86#define ZYNQ_UART_MODE_CHRL_6 0x03U
87#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
88        uint32_t irq_en;
89        uint32_t irq_dis;
90        uint32_t irq_mask;
91        uint32_t irq_sts;
92#define ZYNQ_UART_TOVR BSP_BIT32(12)
93#define ZYNQ_UART_TNFUL BSP_BIT32(11)
94#define ZYNQ_UART_TTRIG BSP_BIT32(10)
95#define ZYNQ_UART_DMSI BSP_BIT32(9)
96#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
97#define ZYNQ_UART_PARE BSP_BIT32(7)
98#define ZYNQ_UART_FRAME BSP_BIT32(6)
99#define ZYNQ_UART_ROVR BSP_BIT32(5)
100#define ZYNQ_UART_TFUL BSP_BIT32(4)
101#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
102#define ZYNQ_UART_RFUL BSP_BIT32(2)
103#define ZYNQ_UART_REMPTY BSP_BIT32(1)
104#define ZYNQ_UART_RTRIG BSP_BIT32(0)
105        uint32_t baud_rate_gen;
106#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
107#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
108#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
109        uint32_t rx_timeout;
110#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
111#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
112#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
113        uint32_t rx_fifo_trg_lvl;
114#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
115#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
116#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
117        uint32_t modem_ctrl;
118#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
119#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
120#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
121        uint32_t modem_sts;
122#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
123#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
124#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
125#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
126#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
127#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
128#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
129#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
130#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
131        uint32_t channel_sts;
132#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
133#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
134#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
135#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
136#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
137#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
138#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
139#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
140#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
141#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
142        uint32_t tx_rx_fifo;
143#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
144#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
145#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
146        uint32_t baud_rate_div;
147#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
148#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
149#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
150        uint32_t flow_delay;
151#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
152#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
153#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
154        uint32_t reserved_3c[2];
155        uint32_t tx_fifo_trg_lvl;
156#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
157#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
158#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
159} zynq_uart;
160
161/** @} */
162
163#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
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