source: rtems/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/**
2 * @file
3 * @ingroup zynq_uart_regs
4 * @brief UART register definitions.
5 */
6
7/*
8 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Dornierstr. 4
12 *  82178 Puchheim
13 *  Germany
14 *  <info@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21/**
22 * @defgroup zynq_uart_regs UART Register Definitions
23 * @ingroup zynq_uart
24 * @brief UART Register Definitions
25 * @{
26 */
27
28#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
29#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
30
31#include <bsp/utility.h>
32
33#define ZYNQ_UART_FIFO_DEPTH 64
34
35typedef struct zynq_uart {
36        uint32_t control;
37#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
38#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
39#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
40#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
41#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
42#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
43#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
44#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
45#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
46        uint32_t mode;
47#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
48#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
49#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
50#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
51#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
52#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
53#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
54#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
55#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
56#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
57#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
58#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
59#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
60#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
61#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
62#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
63#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
64#define ZYNQ_UART_MODE_PAR_ODD 0x01U
65#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
66#define ZYNQ_UART_MODE_PAR_MARK 0x03U
67#define ZYNQ_UART_MODE_PAR_NONE 0x04U
68#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
69#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
70#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
71#define ZYNQ_UART_MODE_CHRL_8 0x00U
72#define ZYNQ_UART_MODE_CHRL_7 0x02U
73#define ZYNQ_UART_MODE_CHRL_6 0x03U
74#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
75        uint32_t irq_en;
76        uint32_t irq_dis;
77        uint32_t irq_mask;
78        uint32_t irq_sts;
79#define ZYNQ_UART_TOVR BSP_BIT32(12)
80#define ZYNQ_UART_TNFUL BSP_BIT32(11)
81#define ZYNQ_UART_TTRIG BSP_BIT32(10)
82#define ZYNQ_UART_DMSI BSP_BIT32(9)
83#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
84#define ZYNQ_UART_PARE BSP_BIT32(7)
85#define ZYNQ_UART_FRAME BSP_BIT32(6)
86#define ZYNQ_UART_ROVR BSP_BIT32(5)
87#define ZYNQ_UART_TFUL BSP_BIT32(4)
88#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
89#define ZYNQ_UART_RFUL BSP_BIT32(2)
90#define ZYNQ_UART_REMPTY BSP_BIT32(1)
91#define ZYNQ_UART_RTRIG BSP_BIT32(0)
92        uint32_t baud_rate_gen;
93#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
94#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
95#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
96        uint32_t rx_timeout;
97#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
98#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
99#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
100        uint32_t rx_fifo_trg_lvl;
101#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
102#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
103#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
104        uint32_t modem_ctrl;
105#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
106#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
107#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
108        uint32_t modem_sts;
109#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
110#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
111#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
112#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
113#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
114#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
115#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
116#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
117#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
118        uint32_t channel_sts;
119#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
120#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
121#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
122#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
123#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
124#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
125#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
126#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
127#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
128#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
129        uint32_t tx_rx_fifo;
130#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
131#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
132#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
133        uint32_t baud_rate_div;
134#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
135#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
136#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
137        uint32_t flow_delay;
138#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
139#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
140#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
141        uint32_t reserved_3c[2];
142        uint32_t tx_fifo_trg_lvl;
143#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
144#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
145#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
146} zynq_uart;
147
148/** @} */
149
150#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
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