1 | /** |
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2 | * @file |
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3 | * @ingroup zynq_interrupt |
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4 | * @brief Interrupt definitions. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * SPDX-License-Identifier: BSD-2-Clause |
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9 | * |
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10 | * Copyright (C) 2013 embedded brains GmbH |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H |
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35 | #define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H |
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36 | |
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37 | #ifndef ASM |
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38 | |
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39 | #include <rtems/irq.h> |
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40 | #include <rtems/irq-extension.h> |
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41 | |
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42 | #include <bsp/arm-a9mpcore-irq.h> |
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43 | #include <dev/irq/arm-gic-irq.h> |
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44 | |
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45 | #ifdef __cplusplus |
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46 | extern "C" { |
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47 | #endif /* __cplusplus */ |
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48 | |
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49 | /** |
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50 | * @defgroup zynq_interrupt Interrupt Support |
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51 | * @ingroup RTEMSBSPsARMZynq |
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52 | * @brief Interrupt Support |
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53 | * @{ |
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54 | */ |
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55 | |
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56 | #define ZYNQ_IRQ_CPU_0 32 |
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57 | #define ZYNQ_IRQ_CPU_1 33 |
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58 | #define ZYNQ_IRQ_L2_CACHE 34 |
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59 | #define ZYNQ_IRQ_OCM 35 |
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60 | #define ZYNQ_IRQ_PMU_0 37 |
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61 | #define ZYNQ_IRQ_PMU_1 38 |
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62 | #define ZYNQ_IRQ_XADC 39 |
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63 | #define ZYNQ_IRQ_DVI 40 |
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64 | #define ZYNQ_IRQ_SWDT 41 |
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65 | #define ZYNQ_IRQ_TTC_0_0 42 |
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66 | #define ZYNQ_IRQ_TTC_1_0 43 |
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67 | #define ZYNQ_IRQ_TTC_2_0 44 |
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68 | #define ZYNQ_IRQ_DMAC_ABORT 45 |
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69 | #define ZYNQ_IRQ_DMAC_0 46 |
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70 | #define ZYNQ_IRQ_DMAC_1 47 |
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71 | #define ZYNQ_IRQ_DMAC_2 48 |
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72 | #define ZYNQ_IRQ_DMAC_3 49 |
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73 | #define ZYNQ_IRQ_SMC 50 |
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74 | #define ZYNQ_IRQ_QUAD_SPI 51 |
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75 | #define ZYNQ_IRQ_GPIO 52 |
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76 | #define ZYNQ_IRQ_USB_0 53 |
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77 | #define ZYNQ_IRQ_ETHERNET_0 54 |
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78 | #define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 |
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79 | #define ZYNQ_IRQ_SDIO_0 56 |
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80 | #define ZYNQ_IRQ_I2C_0 57 |
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81 | #define ZYNQ_IRQ_SPI_0 58 |
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82 | #define ZYNQ_IRQ_UART_0 59 |
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83 | #define ZYNQ_IRQ_CAN_0 60 |
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84 | #define ZYNQ_IRQ_FPGA_0 61 |
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85 | #define ZYNQ_IRQ_FPGA_1 62 |
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86 | #define ZYNQ_IRQ_FPGA_2 63 |
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87 | #define ZYNQ_IRQ_FPGA_3 64 |
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88 | #define ZYNQ_IRQ_FPGA_4 65 |
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89 | #define ZYNQ_IRQ_FPGA_5 66 |
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90 | #define ZYNQ_IRQ_FPGA_6 67 |
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91 | #define ZYNQ_IRQ_FPGA_7 68 |
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92 | #define ZYNQ_IRQ_TTC_0_1 69 |
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93 | #define ZYNQ_IRQ_TTC_1_1 70 |
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94 | #define ZYNQ_IRQ_TTC_2_1 71 |
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95 | #define ZYNQ_IRQ_DMAC_4 72 |
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96 | #define ZYNQ_IRQ_DMAC_5 73 |
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97 | #define ZYNQ_IRQ_DMAC_6 74 |
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98 | #define ZYNQ_IRQ_DMAC_7 75 |
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99 | #define ZYNQ_IRQ_USB_1 76 |
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100 | #define ZYNQ_IRQ_ETHERNET_1 77 |
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101 | #define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 |
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102 | #define ZYNQ_IRQ_SDIO_1 79 |
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103 | #define ZYNQ_IRQ_I2C_1 80 |
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104 | #define ZYNQ_IRQ_SPI_1 81 |
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105 | #define ZYNQ_IRQ_UART_1 82 |
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106 | #define ZYNQ_IRQ_CAN_1 83 |
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107 | #define ZYNQ_IRQ_FPGA_8 84 |
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108 | #define ZYNQ_IRQ_FPGA_9 85 |
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109 | #define ZYNQ_IRQ_FPGA_10 86 |
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110 | #define ZYNQ_IRQ_FPGA_11 87 |
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111 | #define ZYNQ_IRQ_FPGA_12 88 |
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112 | #define ZYNQ_IRQ_FPGA_13 89 |
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113 | #define ZYNQ_IRQ_FPGA_14 90 |
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114 | #define ZYNQ_IRQ_FPGA_15 91 |
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115 | #define ZYNQ_IRQ_PARITY 92 |
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116 | |
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117 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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118 | #define BSP_INTERRUPT_VECTOR_MAX 92 |
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119 | |
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120 | /** @} */ |
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121 | |
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122 | #ifdef __cplusplus |
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123 | } |
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124 | #endif /* __cplusplus */ |
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125 | |
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126 | #endif /* ASM */ |
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127 | |
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128 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ |
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