1 | /** |
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2 | * @file |
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3 | * @ingroup zynq_interrupt |
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4 | * @brief Interrupt definitions. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Dornierstr. 4 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <info@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H |
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22 | #define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H |
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23 | |
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24 | #ifndef ASM |
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25 | |
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26 | #include <rtems/irq.h> |
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27 | #include <rtems/irq-extension.h> |
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28 | |
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29 | #include <bsp/arm-a9mpcore-irq.h> |
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30 | #include <bsp/arm-gic-irq.h> |
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31 | |
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32 | #ifdef __cplusplus |
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33 | extern "C" { |
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34 | #endif /* __cplusplus */ |
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35 | |
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36 | /** |
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37 | * @defgroup zynq_interrupt Interrupt Support |
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38 | * @ingroup arm_zynq |
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39 | * @brief Interrupt Support |
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40 | * @{ |
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41 | */ |
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42 | |
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43 | #define ZYNQ_IRQ_CPU_0 32 |
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44 | #define ZYNQ_IRQ_CPU_1 33 |
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45 | #define ZYNQ_IRQ_L2_CACHE 34 |
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46 | #define ZYNQ_IRQ_OCM 35 |
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47 | #define ZYNQ_IRQ_PMU_0 37 |
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48 | #define ZYNQ_IRQ_PMU_1 38 |
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49 | #define ZYNQ_IRQ_XADC 39 |
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50 | #define ZYNQ_IRQ_DVI 40 |
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51 | #define ZYNQ_IRQ_SWDT 41 |
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52 | #define ZYNQ_IRQ_TTC_0_0 42 |
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53 | #define ZYNQ_IRQ_TTC_1_0 43 |
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54 | #define ZYNQ_IRQ_TTC_2_0 44 |
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55 | #define ZYNQ_IRQ_DMAC_ABORT 45 |
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56 | #define ZYNQ_IRQ_DMAC_0 46 |
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57 | #define ZYNQ_IRQ_DMAC_1 47 |
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58 | #define ZYNQ_IRQ_DMAC_2 48 |
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59 | #define ZYNQ_IRQ_DMAC_3 49 |
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60 | #define ZYNQ_IRQ_SMC 50 |
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61 | #define ZYNQ_IRQ_QUAD_SPI 51 |
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62 | #define ZYNQ_IRQ_GPIO 52 |
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63 | #define ZYNQ_IRQ_USB_0 53 |
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64 | #define ZYNQ_IRQ_ETHERNET_0 54 |
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65 | #define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 |
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66 | #define ZYNQ_IRQ_SDIO_0 56 |
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67 | #define ZYNQ_IRQ_I2C_0 57 |
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68 | #define ZYNQ_IRQ_SPI_0 58 |
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69 | #define ZYNQ_IRQ_UART_0 59 |
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70 | #define ZYNQ_IRQ_CAN_0 60 |
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71 | #define ZYNQ_IRQ_FPGA_0 61 |
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72 | #define ZYNQ_IRQ_FPGA_1 62 |
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73 | #define ZYNQ_IRQ_FPGA_2 63 |
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74 | #define ZYNQ_IRQ_FPGA_3 64 |
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75 | #define ZYNQ_IRQ_FPGA_4 65 |
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76 | #define ZYNQ_IRQ_FPGA_5 66 |
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77 | #define ZYNQ_IRQ_FPGA_6 67 |
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78 | #define ZYNQ_IRQ_FPGA_7 68 |
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79 | #define ZYNQ_IRQ_TTC_0_1 69 |
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80 | #define ZYNQ_IRQ_TTC_1_1 70 |
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81 | #define ZYNQ_IRQ_TTC_2_1 71 |
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82 | #define ZYNQ_IRQ_DMAC_4 72 |
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83 | #define ZYNQ_IRQ_DMAC_5 73 |
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84 | #define ZYNQ_IRQ_DMAC_6 74 |
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85 | #define ZYNQ_IRQ_DMAC_7 75 |
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86 | #define ZYNQ_IRQ_USB_1 76 |
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87 | #define ZYNQ_IRQ_ETHERNET_1 77 |
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88 | #define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 |
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89 | #define ZYNQ_IRQ_SDIO_1 79 |
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90 | #define ZYNQ_IRQ_I2C_1 80 |
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91 | #define ZYNQ_IRQ_SPI_1 81 |
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92 | #define ZYNQ_IRQ_UART_1 82 |
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93 | #define ZYNQ_IRQ_CAN_1 83 |
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94 | #define ZYNQ_IRQ_FPGA_8 84 |
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95 | #define ZYNQ_IRQ_FPGA_9 85 |
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96 | #define ZYNQ_IRQ_FPGA_10 86 |
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97 | #define ZYNQ_IRQ_FPGA_11 87 |
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98 | #define ZYNQ_IRQ_FPGA_12 88 |
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99 | #define ZYNQ_IRQ_FPGA_13 89 |
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100 | #define ZYNQ_IRQ_FPGA_14 90 |
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101 | #define ZYNQ_IRQ_FPGA_15 91 |
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102 | #define ZYNQ_IRQ_PARITY 92 |
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103 | |
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104 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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105 | #define BSP_INTERRUPT_VECTOR_MAX 92 |
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106 | |
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107 | /** @} */ |
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108 | |
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109 | #ifdef __cplusplus |
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110 | } |
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111 | #endif /* __cplusplus */ |
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112 | |
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113 | #endif /* ASM */ |
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114 | |
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115 | #endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ |
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