1 | /* |
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2 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/cadence-i2c.h> |
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16 | #include <bsp/cadence-i2c-regs.h> |
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17 | |
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18 | #include <rtems/irq-extension.h> |
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19 | #include <rtems/score/assert.h> |
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20 | |
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21 | #include <dev/i2c/i2c.h> |
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22 | |
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23 | #define CADENCE_I2C_DIV_A_MAX 4 |
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24 | |
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25 | #define CADENCE_I2C_DIV_B_MAX 64 |
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26 | |
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27 | #define CADENCE_I2C_FIFO_DEPTH 16 |
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28 | |
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29 | #define CADENCE_I2C_DATA_IRQ_DEPTH (CADENCE_I2C_FIFO_DEPTH - 2) |
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30 | |
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31 | #define CADENCE_I2C_TRANSFER_SIZE_MAX 255 |
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32 | |
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33 | #define CADENCE_I2C_TRANSFER_SIZE_ONCE_MAX (18 * CADENCE_I2C_DATA_IRQ_DEPTH) |
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34 | |
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35 | #define CADENCE_I2C_IRQ_ERROR \ |
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36 | (CADENCE_I2C_IXR_ARB_LOST \ |
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37 | | CADENCE_I2C_IXR_RX_UNF \ |
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38 | | CADENCE_I2C_IXR_TX_OVR \ |
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39 | | CADENCE_I2C_IXR_RX_OVR \ |
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40 | | CADENCE_I2C_IXR_NACK) |
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41 | |
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42 | #define CADENCE_I2C_IRQ_USED \ |
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43 | (CADENCE_I2C_IRQ_ERROR \ |
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44 | | CADENCE_I2C_IXR_DATA \ |
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45 | | CADENCE_I2C_IXR_COMP) |
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46 | |
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47 | typedef struct { |
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48 | i2c_bus base; |
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49 | volatile cadence_i2c *regs; |
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50 | i2c_msg *msgs; |
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51 | uint32_t msg_todo; |
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52 | uint32_t current_msg_todo; |
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53 | uint8_t *current_msg_byte; |
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54 | uint32_t current_todo; |
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55 | uint32_t irqstatus; |
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56 | bool read; |
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57 | bool hold; |
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58 | rtems_id task_id; |
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59 | uint32_t input_clock; |
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60 | rtems_vector_number irq; |
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61 | } cadence_i2c_bus; |
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62 | |
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63 | static void cadence_i2c_disable_interrupts(volatile cadence_i2c *regs) |
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64 | { |
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65 | regs->irqdisable = 0xffff; |
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66 | } |
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67 | |
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68 | static void cadence_i2c_clear_irq_status(volatile cadence_i2c *regs) |
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69 | { |
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70 | regs->irqstatus = regs->irqstatus; |
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71 | } |
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72 | |
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73 | static void cadence_i2c_reset(cadence_i2c_bus *bus) |
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74 | { |
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75 | volatile cadence_i2c *regs = bus->regs; |
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76 | uint32_t val; |
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77 | |
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78 | cadence_i2c_disable_interrupts(regs); |
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79 | |
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80 | val = regs->control; |
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81 | val &= ~CADENCE_I2C_CONTROL_HOLD; |
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82 | val |= CADENCE_I2C_CONTROL_ACKEN |
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83 | | CADENCE_I2C_CONTROL_MS |
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84 | | CADENCE_I2C_CONTROL_CLR_FIFO; |
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85 | regs->control = val; |
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86 | |
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87 | regs->transfer_size = 0; |
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88 | regs->status = regs->status; |
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89 | |
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90 | cadence_i2c_clear_irq_status(regs); |
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91 | } |
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92 | |
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93 | static uint32_t cadence_i2c_set_address_size( |
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94 | const i2c_msg *msg, |
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95 | uint32_t control |
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96 | ) |
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97 | { |
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98 | if ((msg->flags & I2C_M_TEN) == 0) { |
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99 | control |= CADENCE_I2C_CONTROL_NEA; |
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100 | } else { |
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101 | control &= ~CADENCE_I2C_CONTROL_NEA; |
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102 | } |
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103 | |
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104 | return control; |
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105 | } |
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106 | |
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107 | static void cadence_i2c_setup_read_transfer( |
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108 | cadence_i2c_bus *bus, |
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109 | volatile cadence_i2c *regs, |
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110 | uint32_t control |
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111 | ) |
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112 | { |
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113 | control |= CADENCE_I2C_CONTROL_RW; |
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114 | regs->control = control; |
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115 | |
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116 | if (bus->current_todo <= CADENCE_I2C_TRANSFER_SIZE_MAX) { |
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117 | regs->transfer_size = bus->current_todo; |
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118 | } else { |
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119 | regs->transfer_size = CADENCE_I2C_TRANSFER_SIZE_ONCE_MAX; |
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120 | } |
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121 | } |
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122 | |
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123 | static void cadence_i2c_next_byte(cadence_i2c_bus *bus) |
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124 | { |
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125 | --bus->current_msg_todo; |
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126 | ++bus->current_msg_byte; |
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127 | |
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128 | if (bus->current_msg_todo == 0) { |
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129 | i2c_msg *msg; |
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130 | |
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131 | ++bus->msgs; |
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132 | --bus->msg_todo; |
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133 | |
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134 | msg = &bus->msgs[0]; |
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135 | |
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136 | bus->current_msg_todo = msg->len; |
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137 | bus->current_msg_byte = msg->buf; |
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138 | } |
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139 | } |
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140 | |
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141 | static void cadence_i2c_write_to_fifo( |
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142 | cadence_i2c_bus *bus, |
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143 | volatile cadence_i2c *regs |
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144 | ) |
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145 | { |
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146 | uint32_t space_available; |
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147 | uint32_t todo_now; |
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148 | uint32_t i; |
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149 | |
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150 | space_available = CADENCE_I2C_FIFO_DEPTH - regs->transfer_size; |
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151 | |
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152 | if (bus->current_todo > space_available) { |
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153 | todo_now = space_available; |
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154 | } else { |
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155 | todo_now = bus->current_todo; |
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156 | } |
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157 | |
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158 | bus->current_todo -= todo_now; |
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159 | |
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160 | for (i = 0; i < todo_now; ++i) { |
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161 | regs->data = *bus->current_msg_byte; |
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162 | |
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163 | cadence_i2c_next_byte(bus); |
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164 | } |
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165 | } |
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166 | |
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167 | static void cadence_i2c_setup_write_transfer( |
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168 | cadence_i2c_bus *bus, |
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169 | volatile cadence_i2c *regs, |
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170 | uint32_t control |
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171 | ) |
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172 | { |
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173 | control &= ~CADENCE_I2C_CONTROL_RW; |
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174 | regs->control = control; |
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175 | |
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176 | cadence_i2c_write_to_fifo(bus, regs); |
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177 | } |
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178 | |
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179 | static void cadence_i2c_setup_transfer( |
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180 | cadence_i2c_bus *bus, |
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181 | volatile cadence_i2c *regs |
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182 | ) |
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183 | { |
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184 | const i2c_msg *msgs = bus->msgs; |
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185 | uint32_t msg_todo = bus->msg_todo; |
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186 | uint32_t i; |
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187 | uint32_t control; |
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188 | |
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189 | bus->current_todo = msgs[0].len; |
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190 | for (i = 1; i < msg_todo && (msgs[i].flags & I2C_M_NOSTART) != 0; ++i) { |
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191 | bus->current_todo += msgs[i].len; |
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192 | } |
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193 | |
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194 | regs = bus->regs; |
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195 | |
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196 | control = regs->control; |
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197 | control |= CADENCE_I2C_CONTROL_CLR_FIFO; |
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198 | |
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199 | bus->hold = i < msg_todo; |
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200 | |
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201 | if (bus->hold || bus->current_todo > CADENCE_I2C_FIFO_DEPTH) { |
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202 | control |= CADENCE_I2C_CONTROL_HOLD; |
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203 | } else { |
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204 | control &= ~CADENCE_I2C_CONTROL_HOLD; |
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205 | } |
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206 | |
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207 | control = cadence_i2c_set_address_size(msgs, control); |
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208 | |
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209 | bus->read = (msgs->flags & I2C_M_RD) != 0; |
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210 | if (bus->read) { |
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211 | cadence_i2c_setup_read_transfer(bus, regs, control); |
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212 | } else { |
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213 | cadence_i2c_setup_write_transfer(bus, regs, control); |
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214 | } |
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215 | |
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216 | cadence_i2c_clear_irq_status(regs); |
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217 | |
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218 | regs->address = CADENCE_I2C_ADDRESS(msgs->addr); |
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219 | } |
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220 | |
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221 | static void cadence_i2c_continue_read_transfer( |
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222 | cadence_i2c_bus *bus, |
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223 | volatile cadence_i2c *regs |
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224 | ) |
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225 | { |
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226 | uint32_t i; |
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227 | |
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228 | bus->current_todo -= CADENCE_I2C_DATA_IRQ_DEPTH; |
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229 | |
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230 | /* |
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231 | * This works since CADENCE_I2C_TRANSFER_SIZE_ONCE_MAX is an integral |
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232 | * multiple of CADENCE_I2C_DATA_IRQ_DEPTH. |
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233 | * |
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234 | * FIXME: Tests with a 1024 byte EEPROM show that this doesn't work. Needs |
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235 | * further investigations with an I2C analyser or an oscilloscope. |
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236 | */ |
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237 | if (regs->transfer_size == 0) { |
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238 | if (bus->current_todo <= CADENCE_I2C_TRANSFER_SIZE_MAX) { |
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239 | regs->transfer_size = bus->current_todo; |
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240 | } else { |
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241 | regs->transfer_size = CADENCE_I2C_TRANSFER_SIZE_ONCE_MAX; |
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242 | } |
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243 | } |
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244 | |
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245 | for (i = 0; i < CADENCE_I2C_DATA_IRQ_DEPTH; ++i) { |
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246 | *bus->current_msg_byte = (uint8_t) regs->data; |
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247 | |
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248 | cadence_i2c_next_byte(bus); |
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249 | } |
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250 | |
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251 | if (!bus->hold && bus->current_todo <= CADENCE_I2C_FIFO_DEPTH) { |
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252 | regs->control &= ~CADENCE_I2C_CONTROL_HOLD; |
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253 | } |
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254 | } |
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255 | |
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256 | static void cadence_i2c_interrupt(void *arg) |
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257 | { |
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258 | cadence_i2c_bus *bus = arg; |
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259 | volatile cadence_i2c *regs = bus->regs; |
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260 | uint32_t irqstatus = regs->irqstatus; |
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261 | bool done = false; |
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262 | |
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263 | /* Clear interrupts */ |
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264 | regs->irqstatus = irqstatus; |
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265 | |
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266 | if ((irqstatus & (CADENCE_I2C_IXR_ARB_LOST | CADENCE_I2C_IXR_NACK)) != 0) { |
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267 | done = true; |
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268 | } |
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269 | |
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270 | if ( |
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271 | (irqstatus & CADENCE_I2C_IXR_DATA) != 0 |
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272 | && bus->read |
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273 | && bus->current_todo >= CADENCE_I2C_DATA_IRQ_DEPTH |
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274 | ) { |
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275 | cadence_i2c_continue_read_transfer(bus, regs); |
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276 | } |
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277 | |
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278 | if ((irqstatus & CADENCE_I2C_IXR_COMP) != 0) { |
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279 | if (bus->read) { |
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280 | uint32_t todo_now = bus->current_todo; |
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281 | uint32_t i; |
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282 | |
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283 | for (i = 0; i < todo_now; ++i) { |
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284 | *bus->current_msg_byte = (uint8_t) regs->data; |
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285 | |
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286 | cadence_i2c_next_byte(bus); |
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287 | } |
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288 | |
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289 | bus->current_todo = 0; |
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290 | |
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291 | done = true; |
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292 | } else { |
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293 | if (bus->current_todo > 0) { |
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294 | cadence_i2c_write_to_fifo(bus, regs); |
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295 | } else { |
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296 | done = true; |
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297 | } |
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298 | |
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299 | if (!bus->hold && bus->current_todo == 0) { |
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300 | regs->control &= ~CADENCE_I2C_CONTROL_HOLD; |
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301 | } |
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302 | } |
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303 | } |
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304 | |
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305 | if (done) { |
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306 | uint32_t err = irqstatus & CADENCE_I2C_IRQ_ERROR; |
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307 | |
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308 | if (bus->msg_todo == 0 || err != 0) { |
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309 | rtems_status_code sc; |
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310 | |
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311 | cadence_i2c_disable_interrupts(regs); |
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312 | |
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313 | bus->irqstatus = err; |
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314 | |
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315 | sc = rtems_event_transient_send(bus->task_id); |
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316 | _Assert(sc == RTEMS_SUCCESSFUL); |
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317 | (void) sc; |
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318 | } else { |
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319 | cadence_i2c_setup_transfer(bus, regs); |
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320 | } |
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321 | } |
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322 | } |
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323 | |
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324 | static int cadence_i2c_transfer( |
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325 | i2c_bus *base, |
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326 | i2c_msg *msgs, |
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327 | uint32_t msg_count |
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328 | ) |
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329 | { |
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330 | cadence_i2c_bus *bus = (cadence_i2c_bus *) base; |
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331 | volatile cadence_i2c *regs; |
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332 | rtems_status_code sc; |
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333 | uint32_t i; |
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334 | |
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335 | _Assert(msg_count > 0); |
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336 | |
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337 | for (i = 0; i < msg_count; ++i) { |
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338 | /* FIXME: Not sure if we can support this. */ |
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339 | if ((msgs[i].flags & I2C_M_RECV_LEN) != 0) { |
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340 | return -EINVAL; |
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341 | } |
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342 | } |
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343 | |
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344 | bus->msgs = &msgs[0]; |
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345 | bus->msg_todo = msg_count; |
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346 | bus->current_msg_todo = msgs[0].len; |
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347 | bus->current_msg_byte = msgs[0].buf; |
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348 | bus->task_id = rtems_task_self(); |
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349 | |
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350 | regs = bus->regs; |
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351 | cadence_i2c_setup_transfer(bus, regs); |
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352 | regs->irqenable = CADENCE_I2C_IRQ_USED; |
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353 | |
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354 | sc = rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout); |
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355 | if (sc != RTEMS_SUCCESSFUL) { |
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356 | cadence_i2c_reset(bus); |
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357 | rtems_event_transient_clear(); |
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358 | |
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359 | return -ETIMEDOUT; |
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360 | } |
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361 | |
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362 | return bus->irqstatus == 0 ? 0 : -EIO; |
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363 | } |
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364 | |
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365 | static int cadence_i2c_set_clock(i2c_bus *base, unsigned long clock) |
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366 | { |
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367 | cadence_i2c_bus *bus = (cadence_i2c_bus *) base; |
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368 | volatile cadence_i2c *regs = bus->regs; |
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369 | uint32_t error = 0xffffffff; |
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370 | uint32_t best_div_a = CADENCE_I2C_DIV_A_MAX - 1; |
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371 | uint32_t best_div_b = CADENCE_I2C_DIV_B_MAX - 1; |
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372 | uint32_t div = bus->input_clock / (22 * clock); |
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373 | uint32_t div_a; |
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374 | uint32_t control; |
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375 | |
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376 | if (div <= 0 || div > (CADENCE_I2C_DIV_A_MAX * CADENCE_I2C_DIV_B_MAX)) { |
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377 | return -EIO; |
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378 | } |
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379 | |
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380 | for (div_a = 0; div_a < CADENCE_I2C_DIV_A_MAX; ++div_a) { |
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381 | uint32_t a = 22 * clock * (div_a + 1); |
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382 | uint32_t b = (bus->input_clock + a - 1) / a; |
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383 | |
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384 | if (b > 0 && b <= CADENCE_I2C_DIV_B_MAX) { |
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385 | uint32_t actual_clock = bus->input_clock / (22 * (div_a + 1) * b); |
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386 | uint32_t e = clock < actual_clock ? |
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387 | actual_clock - clock : clock - actual_clock; |
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388 | |
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389 | /* |
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390 | * Favour greater div_a values according to UG585, Zynq-7000 AP SoC |
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391 | * Technical Reference Manual, Table 20-1: Calculated Values for Standard |
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392 | * and High Speed SCL Clock Values". |
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393 | */ |
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394 | if (e <= error && actual_clock <= clock) { |
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395 | error = e; |
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396 | best_div_a = div_a; |
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397 | best_div_b = b - 1; |
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398 | } |
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399 | } |
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400 | } |
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401 | |
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402 | control = regs->control; |
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403 | control = CADENCE_I2C_CONTROL_DIV_A_SET(control, best_div_a); |
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404 | control = CADENCE_I2C_CONTROL_DIV_B_SET(control, best_div_b); |
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405 | regs->control = control; |
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406 | |
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407 | return 0; |
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408 | } |
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409 | |
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410 | static void cadence_i2c_destroy(i2c_bus *base) |
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411 | { |
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412 | cadence_i2c_bus *bus = (cadence_i2c_bus *) base; |
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413 | rtems_status_code sc; |
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414 | |
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415 | sc = rtems_interrupt_handler_remove(bus->irq, cadence_i2c_interrupt, bus); |
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416 | _Assert(sc == RTEMS_SUCCESSFUL); |
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417 | (void) sc; |
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418 | |
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419 | i2c_bus_destroy_and_free(&bus->base); |
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420 | } |
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421 | |
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422 | int i2c_bus_register_cadence( |
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423 | const char *bus_path, |
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424 | uintptr_t register_base, |
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425 | uint32_t input_clock, |
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426 | rtems_vector_number irq |
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427 | ) |
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428 | { |
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429 | cadence_i2c_bus *bus; |
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430 | rtems_status_code sc; |
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431 | int err; |
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432 | |
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433 | bus = (cadence_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus)); |
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434 | if (bus == NULL) { |
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435 | return -1; |
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436 | } |
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437 | |
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438 | bus->regs = (volatile cadence_i2c *) register_base; |
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439 | bus->input_clock = input_clock; |
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440 | bus->irq = irq; |
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441 | |
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442 | cadence_i2c_reset(bus); |
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443 | |
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444 | err = cadence_i2c_set_clock(&bus->base, I2C_BUS_CLOCK_DEFAULT); |
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445 | if (err != 0) { |
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446 | (*bus->base.destroy)(&bus->base); |
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447 | |
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448 | rtems_set_errno_and_return_minus_one(-err); |
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449 | } |
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450 | |
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451 | sc = rtems_interrupt_handler_install( |
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452 | irq, |
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453 | "Cadence I2C", |
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454 | RTEMS_INTERRUPT_UNIQUE, |
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455 | cadence_i2c_interrupt, |
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456 | bus |
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457 | ); |
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458 | if (sc != RTEMS_SUCCESSFUL) { |
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459 | (*bus->base.destroy)(&bus->base); |
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460 | |
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461 | rtems_set_errno_and_return_minus_one(EIO); |
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462 | } |
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463 | |
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464 | bus->base.transfer = cadence_i2c_transfer; |
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465 | bus->base.set_clock = cadence_i2c_set_clock; |
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466 | bus->base.destroy = cadence_i2c_destroy; |
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467 | |
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468 | return i2c_bus_register(&bus->base, bus_path); |
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469 | } |
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