1 | /* |
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2 | * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/zynq-uart.h> |
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16 | #include <bsp/zynq-uart-regs.h> |
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17 | #include <bsp/irq.h> |
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18 | |
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19 | #include <bspopts.h> |
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20 | |
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21 | /* |
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22 | * Make weak and let the user override. |
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23 | */ |
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24 | uint32_t zynq_uart_input_clock(void) __attribute__ ((weak)); |
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25 | |
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26 | uint32_t zynq_uart_input_clock(void) |
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27 | { |
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28 | return ZYNQ_CLOCK_UART; |
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29 | } |
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30 | |
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31 | static int zynq_cal_baud_rate(uint32_t baudrate, |
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32 | uint32_t* brgr, |
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33 | uint32_t* bauddiv, |
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34 | uint32_t modereg) |
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35 | { |
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36 | uint32_t brgr_value; /* Calculated value for baud rate generator */ |
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37 | uint32_t calcbaudrate; /* Calculated baud rate */ |
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38 | uint32_t bauderror; /* Diff between calculated and requested baud rate */ |
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39 | uint32_t best_error = 0xFFFFFFFF; |
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40 | uint32_t percenterror; |
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41 | uint32_t bdiv; |
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42 | uint32_t inputclk = zynq_uart_input_clock(); |
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43 | |
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44 | /* |
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45 | * Make sure the baud rate is not impossilby large. |
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46 | * Fastest possible baud rate is Input Clock / 2. |
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47 | */ |
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48 | if ((baudrate * 2) > inputclk) { |
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49 | return -1; |
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50 | } |
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51 | /* |
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52 | * Check whether the input clock is divided by 8 |
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53 | */ |
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54 | if(modereg & ZYNQ_UART_MODE_CLKS) { |
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55 | inputclk = inputclk / 8; |
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56 | } |
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57 | |
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58 | /* |
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59 | * Determine the Baud divider. It can be 4to 254. |
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60 | * Loop through all possible combinations |
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61 | */ |
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62 | for (bdiv = 4; bdiv < 255; bdiv++) { |
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63 | |
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64 | /* |
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65 | * Calculate the value for BRGR register |
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66 | */ |
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67 | brgr_value = inputclk / (baudrate * (bdiv + 1)); |
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68 | |
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69 | /* |
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70 | * Calculate the baud rate from the BRGR value |
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71 | */ |
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72 | calcbaudrate = inputclk/ (brgr_value * (bdiv + 1)); |
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73 | |
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74 | /* |
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75 | * Avoid unsigned integer underflow |
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76 | */ |
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77 | if (baudrate > calcbaudrate) { |
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78 | bauderror = baudrate - calcbaudrate; |
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79 | } |
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80 | else { |
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81 | bauderror = calcbaudrate - baudrate; |
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82 | } |
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83 | |
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84 | /* |
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85 | * Find the calculated baud rate closest to requested baud rate. |
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86 | */ |
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87 | if (best_error > bauderror) { |
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88 | *brgr = brgr_value; |
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89 | *bauddiv = bdiv; |
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90 | best_error = bauderror; |
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91 | } |
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92 | } |
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93 | |
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94 | /* |
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95 | * Make sure the best error is not too large. |
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96 | */ |
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97 | percenterror = (best_error * 100) / baudrate; |
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98 | #define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */ |
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99 | if (XUARTPS_MAX_BAUD_ERROR_RATE < percenterror) { |
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100 | return -1; |
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101 | } |
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102 | |
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103 | return 0; |
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104 | } |
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105 | |
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106 | void zynq_uart_initialize(rtems_termios_device_context *base) |
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107 | { |
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108 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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109 | volatile zynq_uart *regs = ctx->regs; |
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110 | uint32_t brgr = 0x3e; |
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111 | uint32_t bauddiv = 0x6; |
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112 | |
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113 | zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, &brgr, &bauddiv, regs->mode); |
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114 | |
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115 | regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); |
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116 | regs->control = ZYNQ_UART_CONTROL_RXDIS |
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117 | | ZYNQ_UART_CONTROL_TXDIS |
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118 | | ZYNQ_UART_CONTROL_RXRES |
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119 | | ZYNQ_UART_CONTROL_TXRES; |
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120 | regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL) |
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121 | | ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE) |
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122 | | ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8); |
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123 | regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr); |
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124 | regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv); |
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125 | regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0); |
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126 | regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0); |
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127 | regs->control = ZYNQ_UART_CONTROL_RXEN |
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128 | | ZYNQ_UART_CONTROL_TXEN |
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129 | | ZYNQ_UART_CONTROL_RSTTO; |
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130 | } |
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131 | |
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132 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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133 | static void zynq_uart_interrupt(void *arg) |
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134 | { |
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135 | rtems_termios_tty *tty = arg; |
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136 | zynq_uart_context *ctx = rtems_termios_get_device_context(tty); |
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137 | volatile zynq_uart *regs = ctx->regs; |
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138 | uint32_t channel_sts; |
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139 | |
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140 | if ((regs->irq_sts & (ZYNQ_UART_TIMEOUT | ZYNQ_UART_RTRIG)) != 0) { |
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141 | regs->irq_sts = ZYNQ_UART_TIMEOUT | ZYNQ_UART_RTRIG; |
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142 | |
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143 | do { |
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144 | char c = (char) ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo); |
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145 | |
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146 | rtems_termios_enqueue_raw_characters(tty, &c, 1); |
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147 | |
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148 | channel_sts = regs->channel_sts; |
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149 | } while ((channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) == 0); |
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150 | } else { |
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151 | channel_sts = regs->channel_sts; |
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152 | } |
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153 | |
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154 | if (ctx->transmitting && (channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) != 0) { |
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155 | rtems_termios_dequeue_characters(tty, 1); |
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156 | } |
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157 | } |
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158 | #endif |
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159 | |
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160 | static bool zynq_uart_first_open( |
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161 | rtems_termios_tty *tty, |
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162 | rtems_termios_device_context *base, |
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163 | struct termios *term, |
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164 | rtems_libio_open_close_args_t *args |
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165 | ) |
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166 | { |
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167 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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168 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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169 | volatile zynq_uart *regs = ctx->regs; |
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170 | rtems_status_code sc; |
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171 | #endif |
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172 | |
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173 | rtems_termios_set_initial_baud(tty, ZYNQ_UART_DEFAULT_BAUD); |
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174 | zynq_uart_initialize(base); |
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175 | |
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176 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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177 | regs->rx_timeout = 32; |
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178 | regs->rx_fifo_trg_lvl = ZYNQ_UART_FIFO_DEPTH / 2; |
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179 | regs->irq_dis = 0xffffffff; |
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180 | regs->irq_sts = 0xffffffff; |
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181 | regs->irq_en = ZYNQ_UART_RTRIG | ZYNQ_UART_TIMEOUT; |
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182 | sc = rtems_interrupt_handler_install( |
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183 | ctx->irq, |
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184 | "UART", |
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185 | RTEMS_INTERRUPT_SHARED, |
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186 | zynq_uart_interrupt, |
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187 | tty |
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188 | ); |
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189 | if (sc != RTEMS_SUCCESSFUL) { |
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190 | return false; |
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191 | } |
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192 | #endif |
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193 | |
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194 | return true; |
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195 | } |
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196 | |
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197 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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198 | static void zynq_uart_last_close( |
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199 | rtems_termios_tty *tty, |
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200 | rtems_termios_device_context *base, |
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201 | rtems_libio_open_close_args_t *args |
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202 | ) |
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203 | { |
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204 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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205 | |
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206 | rtems_interrupt_handler_remove(ctx->irq, zynq_uart_interrupt, tty); |
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207 | } |
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208 | #endif |
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209 | |
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210 | int zynq_uart_read_polled(rtems_termios_device_context *base) |
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211 | { |
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212 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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213 | volatile zynq_uart *regs = ctx->regs; |
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214 | |
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215 | if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) { |
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216 | return -1; |
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217 | } else { |
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218 | return ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo); |
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219 | } |
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220 | } |
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221 | |
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222 | void zynq_uart_write_polled( |
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223 | rtems_termios_device_context *base, |
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224 | char c |
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225 | ) |
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226 | { |
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227 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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228 | volatile zynq_uart *regs = ctx->regs; |
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229 | |
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230 | while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TFUL) != 0) { |
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231 | /* Wait */ |
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232 | } |
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233 | |
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234 | regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c); |
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235 | } |
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236 | |
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237 | static void zynq_uart_write_support( |
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238 | rtems_termios_device_context *base, |
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239 | const char *buf, |
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240 | size_t len |
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241 | ) |
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242 | { |
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243 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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244 | zynq_uart_context *ctx = (zynq_uart_context *) base; |
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245 | volatile zynq_uart *regs = ctx->regs; |
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246 | |
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247 | if (len > 0) { |
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248 | ctx->transmitting = true; |
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249 | regs->irq_sts = ZYNQ_UART_TEMPTY; |
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250 | regs->irq_en = ZYNQ_UART_TEMPTY; |
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251 | regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(buf[0]); |
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252 | } else { |
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253 | ctx->transmitting = false; |
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254 | regs->irq_dis = ZYNQ_UART_TEMPTY; |
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255 | } |
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256 | #else |
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257 | ssize_t i; |
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258 | |
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259 | for (i = 0; i < len; ++i) { |
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260 | zynq_uart_write_polled(base, buf[i]); |
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261 | } |
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262 | #endif |
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263 | } |
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264 | |
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265 | static bool zynq_uart_set_attributes( |
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266 | rtems_termios_device_context *context, |
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267 | const struct termios *term |
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268 | ) |
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269 | { |
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270 | #if 0 |
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271 | volatile zynq_uart *regs = zynq_uart_get_regs(minor); |
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272 | uint32_t brgr = 0; |
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273 | uint32_t bauddiv = 0; |
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274 | int rc; |
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275 | |
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276 | rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode); |
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277 | if (rc != 0) |
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278 | return rc; |
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279 | |
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280 | regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); |
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281 | regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr); |
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282 | regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv); |
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283 | regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN; |
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284 | |
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285 | return true; |
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286 | #else |
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287 | return false; |
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288 | #endif |
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289 | } |
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290 | |
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291 | const rtems_termios_device_handler zynq_uart_handler = { |
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292 | .first_open = zynq_uart_first_open, |
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293 | .set_attributes = zynq_uart_set_attributes, |
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294 | .write = zynq_uart_write_support, |
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295 | #ifdef ZYNQ_CONSOLE_USE_INTERRUPTS |
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296 | .last_close = zynq_uart_last_close, |
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297 | .mode = TERMIOS_IRQ_DRIVEN |
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298 | #else |
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299 | .poll_read = zynq_uart_read_polled, |
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300 | .mode = TERMIOS_POLLED |
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301 | #endif |
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302 | }; |
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303 | |
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304 | void zynq_uart_reset_tx_flush(zynq_uart_context *ctx) |
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305 | { |
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306 | volatile zynq_uart *regs = ctx->regs; |
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307 | int c = 4; |
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308 | |
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309 | while (c-- > 0) |
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310 | zynq_uart_write_polled(&ctx->base, '\r'); |
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311 | |
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312 | while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) == 0) { |
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313 | /* Wait */ |
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314 | } |
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315 | } |
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