1 | /** |
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2 | * @file tms570_selftest.c |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief TMS570 selftest support functions implementation. |
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7 | */ |
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8 | /* |
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9 | * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com |
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10 | * |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * |
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16 | * Redistributions of source code must retain the above copyright |
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17 | * notice, this list of conditions and the following disclaimer. |
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18 | * |
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19 | * Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the |
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22 | * distribution. |
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23 | * |
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24 | * Neither the name of Texas Instruments Incorporated nor the names of |
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25 | * its contributors may be used to endorse or promote products derived |
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26 | * from this software without specific prior written permission. |
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27 | * |
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28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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39 | * |
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40 | */ |
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41 | |
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42 | #include <stdint.h> |
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43 | #include <stdbool.h> |
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44 | #include <stddef.h> |
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45 | #include <bsp/tms570.h> |
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46 | #include "tms570_selftest.h" |
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47 | #include "tms570_hwinit.h" |
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48 | |
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49 | /** |
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50 | * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest). |
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51 | / |
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52 | * @return 1 if EFUSE Stuck at zero test completed, otherwise 0. |
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53 | * |
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54 | * Checks to see if the EFUSE Stuck at zero test is completed successfully. |
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55 | */ |
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56 | /* SourceId : SELFTEST_SourceId_012 */ |
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57 | /* DesignId : SELFTEST_DesignId_014 */ |
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58 | /* Requirements : HL_SR402 */ |
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59 | bool tms570_efc_stuck_zero( void ) |
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60 | { |
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61 | uint32_t esm_estatus4, esm_estatus1; |
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62 | |
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63 | bool result = false; |
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64 | |
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65 | uint32_t output_enable = TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE | |
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66 | TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE | |
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67 | TMS570_EFUSE_EFCBOUND_Instruction_Error_OE | |
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68 | TMS570_EFUSE_EFCBOUND_Autoload_Error_OE; |
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69 | |
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70 | uint32_t error_checks = TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error | |
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71 | TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error | |
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72 | TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error | |
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73 | TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error; |
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74 | |
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75 | /* configure the output enable for auto load error , instruction info, |
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76 | instruction error, and self test error using boundary register |
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77 | and drive values one across all the errors */ |
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78 | TMS570_EFUSE.EFCBOUND = output_enable | error_checks; |
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79 | |
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80 | /* Read from the pin register. This register holds the current values |
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81 | of above errors. This value should be 0x5c00.If not at least one of |
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82 | the above errors is stuck at 0. */ |
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83 | if ( ( TMS570_EFUSE.EFCPINS & 0x5C00U ) == 0x5C00U ) { |
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84 | esm_estatus4 = TMS570_ESM.SR4; |
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85 | esm_estatus1 = TMS570_ESM.SR[ 2U ]; |
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86 | |
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87 | /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */ |
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88 | if ( ( ( esm_estatus4 & 0x200U ) == 0x200U ) && |
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89 | ( ( esm_estatus1 & 0x2U ) == 0x2U ) ) { |
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90 | /* stuck-at-zero test passed */ |
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91 | result = true; |
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92 | } |
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93 | } |
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94 | |
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95 | /* put the pins back low */ |
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96 | TMS570_EFUSE.EFCBOUND = output_enable; |
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97 | |
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98 | /* clear group1 flag */ |
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99 | TMS570_ESM.SR4 = 0x200U; |
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100 | |
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101 | /* clear group3 flag */ |
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102 | TMS570_ESM.SR[ 2U ] = 0x2U; |
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103 | |
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104 | /* The nERROR pin will become inactive once the LTC counter expires */ |
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105 | TMS570_ESM.EKR = 0x5U; |
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106 | |
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107 | return result; |
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108 | } |
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109 | |
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110 | /** |
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111 | * @brief EFUSE module self check Driver (HCG:efcSelfTest) |
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112 | * |
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113 | * This function self checks the EFSUE module. |
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114 | */ |
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115 | /* SourceId : SELFTEST_SourceId_013 */ |
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116 | /* DesignId : SELFTEST_DesignId_013 */ |
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117 | /* Requirements : HL_SR402 */ |
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118 | void tms570_efc_self_test( void ) |
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119 | { |
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120 | /* configure self-test cycles */ |
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121 | TMS570_EFUSE.EFC_ST_CY = 0x258U; |
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122 | |
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123 | /* configure self-test signature */ |
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124 | TMS570_EFUSE.EFC_ST_SIG = 0x5362F97FU; |
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125 | |
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126 | /* configure boundary register to start ECC self-test */ |
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127 | TMS570_EFUSE.EFCBOUND = 0x00002000 | |
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128 | TMS570_EFUSE_EFCBOUND_Input_Enable( 0xF ); |
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129 | } |
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130 | |
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131 | /** |
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132 | * @brief EFUSE module self check Driver (HCG:checkefcSelfTest) |
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133 | * |
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134 | * @return Returns TRUE if EFC Selftest was a PASS, else FALSE |
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135 | * |
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136 | * This function returns the status of efcSelfTest. |
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137 | * Note: This function can be called only after calling efcSelfTest |
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138 | */ |
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139 | /* SourceId : SELFTEST_SourceId_014 */ |
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140 | /* DesignId : SELFTEST_DesignId_015 */ |
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141 | /* Requirements : HL_SR403 */ |
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142 | bool tms570_efc_check_self_test( void ) |
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143 | { |
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144 | bool result = false; |
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145 | |
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146 | uint32_t efc_pins, efc_error; |
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147 | uint32_t esmCh40Stat, esmCh41Stat = 0U; |
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148 | |
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149 | /* wait until EFC self-test is done */ |
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150 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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151 | while ( ( TMS570_EFUSE.EFCPINS & TMS570_EFUSE_EFCPINS_EFC_Selftest_Done ) == |
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152 | 0U ) { |
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153 | } /* Wait */ |
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154 | |
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155 | /* check if EFC self-test error occurred */ |
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156 | efc_pins = TMS570_EFUSE.EFCPINS; |
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157 | efc_error = TMS570_EFUSE.EFC_ERR_STAT; |
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158 | |
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159 | if ( ( ( efc_pins & TMS570_EFUSE_EFCPINS_EFC_Selftest_Error ) == 0U ) && |
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160 | ( ( efc_error & 0x1FU ) == 0U ) ) { |
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161 | /* check if EFC self-test error is set */ |
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162 | esmCh40Stat = TMS570_ESM.SR4 & 0x100U; |
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163 | esmCh41Stat = TMS570_ESM.SR4 & 0x200U; |
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164 | |
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165 | if ( ( esmCh40Stat == 0U ) && ( esmCh41Stat == 0U ) ) { |
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166 | result = true; |
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167 | } |
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168 | } |
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169 | |
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170 | return result; |
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171 | } |
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172 | |
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173 | /** |
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174 | * @brief EFUSE module self check Driver (HCG:efcCheck) |
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175 | * @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed |
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176 | * 1 if no error was detected during autoload but Stuck At Zero Test failed |
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177 | * 2 if there was a single-bit error detected during autoload |
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178 | * 3 if some other error occurred during autoload |
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179 | * |
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180 | * This function self checks the EFUSE module. |
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181 | */ |
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182 | /* SourceId : SELFTEST_SourceId_011 */ |
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183 | /* DesignId : SELFTEST_DesignId_012 */ |
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184 | /* Requirements : HL_SR402 */ |
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185 | uint32_t tms570_efc_check( void ) |
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186 | { |
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187 | uint32_t efc_status = 0U; |
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188 | uint32_t status; |
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189 | |
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190 | /* read the EFC Error Status Register */ |
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191 | efc_status = TMS570_EFUSE.EFC_ERR_STAT; |
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192 | |
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193 | if ( efc_status == 0x0U ) { |
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194 | /* run stuck-at-zero test and check if it passed */ |
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195 | if ( tms570_efc_stuck_zero() == true ) { |
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196 | /* start EFC ECC logic self-test */ |
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197 | tms570_efc_self_test(); |
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198 | status = 0U; |
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199 | } else { |
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200 | /* EFC output is stuck-at-zero, device operation unreliable */ |
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201 | bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); |
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202 | status = 1U; |
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203 | } |
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204 | } |
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205 | /* EFC Error Register is not zero */ |
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206 | else { |
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207 | /* one-bit error detected during autoload */ |
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208 | if ( efc_status == 0x15U ) { |
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209 | /* start EFC ECC logic self-test */ |
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210 | tms570_efc_self_test(); |
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211 | status = 2U; |
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212 | } else { |
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213 | /* Some other EFC error was detected */ |
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214 | bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); |
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215 | status = 3U; |
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216 | } |
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217 | } |
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218 | |
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219 | return status; |
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220 | } |
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221 | |
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222 | /** |
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223 | * @brief PBIST self test Driver (HCG:pbistSelfCheck) |
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224 | * |
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225 | * This function is called to perform PBIST self test. |
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226 | */ |
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227 | /* SourceId : SELFTEST_SourceId_005 */ |
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228 | /* DesignId : SELFTEST_DesignId_005 */ |
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229 | /* Requirements : HL_SR399 */ |
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230 | void tms570_pbist_self_check( void ) |
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231 | { |
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232 | volatile uint32_t i = 0U; |
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233 | uint32_t PBIST_wait_done_loop = 0U; |
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234 | |
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235 | /* Run a diagnostic check on the memory self-test controller */ |
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236 | /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */ |
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237 | |
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238 | /* Disable PBIST clocks and ROM clock */ |
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239 | TMS570_PBIST.PACT = 0x0U; |
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240 | |
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241 | /* PBIST ROM clock frequency = HCLK frequency /2 */ |
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242 | /* Disable memory self controller */ |
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243 | TMS570_SYS1.MSTGCR = 0x00000105U; |
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244 | |
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245 | /* Disable Memory Initialization controller */ |
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246 | TMS570_SYS1.MINITGCR = 0x5U; |
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247 | |
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248 | /* Enable memory self controller */ |
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249 | TMS570_SYS1.MSTGCR = 0x0000010AU; |
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250 | |
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251 | /* Clear PBIST Done */ |
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252 | TMS570_SYS1.MSTCGSTAT = 0x1U; |
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253 | |
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254 | /* Enable PBIST controller */ |
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255 | TMS570_SYS1.MSIENA = 0x1U; |
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256 | |
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257 | /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ |
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258 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ |
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259 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ |
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260 | for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ |
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261 | } |
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262 | |
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263 | /* Enable PBIST clocks and ROM clock */ |
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264 | TMS570_PBIST.PACT = 0x3U; |
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265 | |
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266 | /* CPU control of PBIST */ |
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267 | TMS570_PBIST.DLR = 0x10U; |
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268 | |
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269 | /* Custom always fail algo, this will not use the ROM and just set a fail */ |
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270 | TMS570_PBIST.RAMT = 0x00002000U; |
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271 | *(volatile uint32_t *) 0xFFFFE400U = 0x4C000001U; |
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272 | *(volatile uint32_t *) 0xFFFFE440U = 0x00000075U; |
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273 | *(volatile uint32_t *) 0xFFFFE404U = 0x4C000002U; |
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274 | *(volatile uint32_t *) 0xFFFFE444U = 0x00000075U; |
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275 | *(volatile uint32_t *) 0xFFFFE408U = 0x4C000003U; |
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276 | *(volatile uint32_t *) 0xFFFFE448U = 0x00000075U; |
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277 | *(volatile uint32_t *) 0xFFFFE40CU = 0x4C000004U; |
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278 | *(volatile uint32_t *) 0xFFFFE44CU = 0x00000075U; |
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279 | *(volatile uint32_t *) 0xFFFFE410U = 0x4C000005U; |
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280 | *(volatile uint32_t *) 0xFFFFE450U = 0x00000075U; |
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281 | *(volatile uint32_t *) 0xFFFFE414U = 0x4C000006U; |
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282 | *(volatile uint32_t *) 0xFFFFE454U = 0x00000075U; |
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283 | *(volatile uint32_t *) 0xFFFFE418U = 0x00000000U; |
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284 | *(volatile uint32_t *) 0xFFFFE458U = 0x00000001U; |
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285 | |
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286 | /* PBIST_RUN */ |
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287 | ( &TMS570_PBIST.DLR )[ 2 ] = 1; |
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288 | |
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289 | /* wait until memory self-test done is indicated */ |
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290 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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291 | while ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0x1U ) |
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292 | PBIST_wait_done_loop++; |
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293 | |
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294 | /* Wait */ |
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295 | |
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296 | /* Check for the failure */ |
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297 | if ( ( TMS570_PBIST.FSRF0 & 0x1U ) != 0x1U ) { |
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298 | /* No failure was indicated even if the always fail algorithm was run*/ |
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299 | bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL1 ); |
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300 | } else { |
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301 | /* Check that the algorithm executed in the expected amount of time. */ |
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302 | /* This time is dependent on the ROMCLKDIV selected above */ |
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303 | if ( PBIST_wait_done_loop >= 2U ) { |
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304 | bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL2 ); |
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305 | } |
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306 | |
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307 | /* Disable PBIST clocks and ROM clock */ |
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308 | TMS570_PBIST.PACT = 0x0U; |
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309 | |
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310 | /* Disable PBIST */ |
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311 | TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U; |
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312 | TMS570_SYS1.MSTGCR |= 0x5U; |
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313 | } |
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314 | } |
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315 | |
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316 | /** |
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317 | * @brief CPU self test Driver (HCG:pbistRun) |
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318 | * @param[in] raminfoL - Select the list of RAM to be tested. |
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319 | * @param[in] algomask - Select the list of Algorithm to be run. |
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320 | * |
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321 | * This function performs Memory Built-in Self test using PBIST module. |
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322 | */ |
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323 | /* SourceId : SELFTEST_SourceId_006 */ |
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324 | /* DesignId : SELFTEST_DesignId_006 */ |
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325 | /* Requirements : HL_SR400 */ |
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326 | void tms570_pbist_run( |
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327 | uint32_t raminfoL, |
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328 | uint32_t algomask |
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329 | ) |
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330 | { |
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331 | volatile uint32_t i = 0U; |
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332 | |
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333 | /* PBIST ROM clock frequency = HCLK frequency /2 */ |
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334 | /* Disable memory self controller */ |
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335 | TMS570_SYS1.MSTGCR = 0x00000105U; |
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336 | |
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337 | /* Disable Memory Initialization controller */ |
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338 | TMS570_SYS1.MINITGCR = 0x5U; |
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339 | |
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340 | /* Enable PBIST controller */ |
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341 | TMS570_SYS1.MSIENA = 0x1U; |
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342 | |
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343 | /* Enable memory self controller */ |
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344 | TMS570_SYS1.MSTGCR = 0x0000010AU; |
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345 | |
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346 | /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ |
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347 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ |
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348 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ |
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349 | for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ |
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350 | } |
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351 | |
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352 | /* Enable PBIST clocks and ROM clock */ |
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353 | TMS570_PBIST.PACT = 0x3U; |
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354 | |
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355 | /* Select all algorithms to be tested */ |
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356 | TMS570_PBIST.ALGO = algomask; |
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357 | |
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358 | /* Select RAM groups */ |
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359 | TMS570_PBIST.RINFOL = raminfoL; |
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360 | |
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361 | /* Select all RAM groups */ |
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362 | TMS570_PBIST.RINFOUL = 0x00000000U; |
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363 | |
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364 | /* ROM contents will not override RINFOx settings */ |
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365 | TMS570_PBIST.OVER = 0x0U; |
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366 | |
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367 | /* Algorithm code is loaded from ROM */ |
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368 | TMS570_PBIST.ROM = 0x3U; |
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369 | |
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370 | /* Start PBIST */ |
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371 | TMS570_PBIST.DLR = 0x14U; |
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372 | } |
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373 | |
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374 | /** |
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375 | * @brief Routine to stop PBIST test enabled (HCG:pbistStop) |
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376 | * |
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377 | * This function is called to stop PBIST after test is performed. |
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378 | */ |
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379 | /* SourceId : SELFTEST_SourceId_007 */ |
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380 | /* DesignId : SELFTEST_DesignId_007 */ |
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381 | /* Requirements : HL_SR523 */ |
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382 | void tms570_pbist_stop( void ) |
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383 | { |
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384 | /* disable pbist clocks and ROM clock */ |
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385 | TMS570_PBIST.PACT = 0x0U; |
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386 | TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U; |
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387 | TMS570_SYS1.MSTGCR |= 0x5U; |
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388 | } |
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389 | |
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390 | /** |
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391 | * @brief Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted) |
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392 | * @return 1 if PBIST test completed, otherwise 0. |
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393 | * |
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394 | * Checks to see if the PBIST test is completed. |
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395 | */ |
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396 | /* SourceId : SELFTEST_SourceId_008 */ |
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397 | /* DesignId : SELFTEST_DesignId_008 */ |
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398 | /* Requirements : HL_SR401 */ |
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399 | bool tms570_pbist_is_test_completed( void ) |
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400 | { |
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401 | return ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0U ); |
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402 | } |
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403 | |
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404 | /** |
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405 | * @brief Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed) |
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406 | * @return 1 if PBIST test passed, otherwise 0. |
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407 | * |
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408 | * Checks to see if the PBIST test is completed successfully. |
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409 | */ |
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410 | /* SourceId : SELFTEST_SourceId_009 */ |
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411 | /* DesignId : SELFTEST_DesignId_009 */ |
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412 | /* Requirements : HL_SR401 */ |
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413 | bool tms570_pbist_is_test_passed( void ) |
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414 | { |
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415 | bool status; |
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416 | |
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417 | if ( TMS570_PBIST.FSRF0 == 0U ) { |
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418 | status = true; |
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419 | } else { |
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420 | status = false; |
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421 | } |
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422 | |
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423 | return status; |
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424 | } |
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425 | |
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426 | /** |
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427 | * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus) |
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428 | * @param[in] port - Select the port to get the status. |
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429 | * @return 1 if PBIST Port test completed successfully, otherwise 0. |
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430 | * |
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431 | * Checks to see if the selected PBIST Port test is completed successfully. |
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432 | */ |
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433 | /* SourceId : SELFTEST_SourceId_010 */ |
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434 | /* DesignId : SELFTEST_DesignId_010 */ |
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435 | /* Requirements : HL_SR401 */ |
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436 | bool tms570_pbist_port_test_status( uint32_t port ) |
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437 | { |
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438 | bool status; |
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439 | |
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440 | if ( port == (uint32_t) PBIST_PORT0 ) { |
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441 | status = ( TMS570_PBIST.FSRF0 == 0U ); |
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442 | } else { |
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443 | /* Invalid Input */ |
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444 | status = false; |
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445 | } |
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446 | |
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447 | return status; |
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448 | } |
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449 | |
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450 | /** |
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451 | * @brief Reaction to PBIST failure (HCG:pbistFail) |
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452 | * |
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453 | * @return Void. |
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454 | */ |
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455 | /* SourceId : SELFTEST_SourceId_042 */ |
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456 | /* DesignId : SELFTEST_DesignId_011 */ |
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457 | /* Requirements : HL_SR401 */ |
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458 | void tms570_pbist_fail( void ) |
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459 | { |
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460 | uint32_t PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0; |
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461 | |
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462 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ |
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463 | PBIST_RAMT = TMS570_PBIST.RAMT; |
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464 | PBIST_FSRA0 = TMS570_PBIST.FSRA0; |
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465 | PBIST_FSRDL0 = TMS570_PBIST.FSRDL0; |
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466 | |
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467 | if ( tms570_pbist_port_test_status( (uint32_t) PBIST_PORT0 ) != true ) { |
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468 | uint32_t groupSelect = ( PBIST_RAMT & 0xFF000000U ) >> 24U; |
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469 | uint32_t dataSelect = ( PBIST_RAMT & 0x00FF0000U ) >> 16U; |
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470 | uint32_t address = PBIST_FSRA0; |
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471 | uint32_t data = PBIST_FSRDL0; |
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472 | tms570_memory_port0_fail_notification( groupSelect, |
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473 | dataSelect, |
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474 | address, |
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475 | data ); |
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476 | } else { |
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477 | /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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478 | /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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479 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ |
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480 | for (;; ) { |
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481 | } /* Wait */ |
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482 | } |
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483 | } |
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484 | |
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485 | /** |
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486 | * @brief Memory Initialization Driver (HCG:memoryInit) |
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487 | * |
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488 | * This function is called to perform Memory initialization of selected RAM's. |
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489 | */ |
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490 | /* SourceId : SELFTEST_SourceId_002 */ |
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491 | /* DesignId : SELFTEST_DesignId_004 */ |
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492 | /* Requirements : HL_SR396 */ |
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493 | void tms570_memory_init( uint32_t ram ) |
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494 | { |
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495 | /* Enable Memory Hardware Initialization */ |
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496 | TMS570_SYS1.MINITGCR = 0xAU; |
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497 | |
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498 | /* Enable Memory Hardware Initialization for selected RAM's */ |
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499 | TMS570_SYS1.MSIENA = ram; |
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500 | |
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501 | /* Wait until Memory Hardware Initialization complete */ |
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502 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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503 | while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) { |
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504 | } /* Wait */ |
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505 | |
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506 | /* Disable Memory Hardware Initialization */ |
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507 | TMS570_SYS1.MINITGCR = 0x5U; |
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508 | } |
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509 | |
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510 | volatile uint32_t *const |
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511 | tms570_esm_group_channel_to_sr_table[ 4 ][ 2 ] = { |
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512 | { NULL, NULL }, |
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513 | { &TMS570_ESM.SR[ 0 ], &TMS570_ESM.SR4 }, |
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514 | { &TMS570_ESM.SR[ 1 ], NULL }, |
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515 | { &TMS570_ESM.SR[ 2 ], NULL }, |
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516 | }; |
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517 | |
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518 | /** |
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519 | * @brief Routine to clear specified error channel signalling bit |
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520 | * @param[in] grp - ESM error channels group |
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521 | * @param[in] chan - ESM error channel number inside specified group |
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522 | */ |
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523 | void tms570_esm_channel_sr_clear( |
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524 | unsigned grp, |
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525 | unsigned chan |
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526 | ) |
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527 | { |
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528 | volatile uint32_t *sr_reg; |
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529 | |
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530 | sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ]; |
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531 | |
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532 | if ( sr_reg != NULL ) |
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533 | *sr_reg = 1 << (chan & 0x1f); |
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534 | } |
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535 | |
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536 | /** tms570_esm_channel_sr_get |
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537 | * @brief Routine to test is specified error channel is signalling error |
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538 | * @param[in] grp - ESM error channels group |
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539 | * @param[in] chan - ESM error channel number inside specified group |
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540 | */ |
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541 | int tms570_esm_channel_sr_get( |
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542 | unsigned grp, |
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543 | unsigned chan |
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544 | ) |
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545 | { |
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546 | volatile uint32_t *sr_reg; |
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547 | |
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548 | sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ]; |
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549 | |
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550 | if ( sr_reg != NULL ) |
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551 | return *sr_reg & ( 1 << ( chan & 0x1f ) ); |
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552 | else |
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553 | return 0; |
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554 | } |
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555 | |
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556 | /** |
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557 | * @brief Enable peripheral RAM parity (HCG:enableParity) |
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558 | * |
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559 | * This function enables RAM parity for all peripherals for which RAM parity check is enabled. |
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560 | * This function is called before memoryInit in the startup |
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561 | * |
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562 | */ |
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563 | void tms570_enable_parity( void ) |
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564 | { |
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565 | TMS570_DMA.DMAPCR = 0xAU; /* Enable DMA RAM parity */ |
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566 | TMS570_VIM.PARCTL = 0xAU; /* Enable VIM RAM parity */ |
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567 | TMS570_DCAN1.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */ |
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568 | TMS570_DCAN2.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */ |
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569 | TMS570_DCAN3.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN3 RAM parity */ |
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570 | TMS570_ADC1.PARCR = 0xAU; /* Enable ADC1 RAM parity */ |
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571 | TMS570_ADC2.PARCR = 0xAU; /* Enable ADC2 RAM parity */ |
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572 | TMS570_NHET1.PCR = 0xAU; /* Enable HET1 RAM parity */ |
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573 | TMS570_HTU1.PCR = 0xAU; /* Enable HTU1 RAM parity */ |
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574 | TMS570_NHET2.PCR = 0xAU; /* Enable HET2 RAM parity */ |
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575 | TMS570_HTU2.PCR = 0xAU; /* Enable HTU2 RAM parity */ |
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576 | } |
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577 | |
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578 | /** |
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579 | * @brief Disable peripheral RAM parity (HCG:disableParity) |
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580 | * |
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581 | * This function disables RAM parity for all peripherals for which RAM parity check is enabled. |
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582 | * This function is called after memoryInit in the startup |
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583 | * |
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584 | */ |
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585 | void tms570_disable_parity( void ) |
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586 | { |
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587 | TMS570_DMA.DMAPCR = 0x5U; /* Disable DMA RAM parity */ |
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588 | TMS570_VIM.PARCTL = 0x5U; /* Disable VIM RAM parity */ |
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589 | TMS570_DCAN1.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */ |
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590 | TMS570_DCAN2.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */ |
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591 | TMS570_DCAN3.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN3 RAM parity */ |
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592 | TMS570_ADC1.PARCR = 0x5U; /* Disable ADC1 RAM parity */ |
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593 | TMS570_ADC2.PARCR = 0x5U; /* Disable ADC2 RAM parity */ |
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594 | TMS570_NHET1.PCR = 0x5U; /* Disable HET1 RAM parity */ |
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595 | TMS570_HTU1.PCR = 0x5U; /* Disable HTU1 RAM parity */ |
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596 | TMS570_NHET2.PCR = 0x5U; /* Disable HET2 RAM parity */ |
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597 | TMS570_HTU2.PCR = 0x5U; /* Disable HTU2 RAM parity */ |
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598 | } |
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