1 | /** @file init_system.c |
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2 | |
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3 | based on Ti HalCoGen generated file |
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4 | */ |
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5 | |
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6 | /* |
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7 | * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com |
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8 | * |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions |
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12 | * are met: |
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13 | * |
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14 | * Redistributions of source code must retain the above copyright |
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15 | * notice, this list of conditions and the following disclaimer. |
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16 | * |
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17 | * Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the |
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20 | * distribution. |
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21 | * |
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22 | * Neither the name of Texas Instruments Incorporated nor the names of |
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23 | * its contributors may be used to endorse or promote products derived |
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24 | * from this software without specific prior written permission. |
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25 | * |
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26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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27 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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28 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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29 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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30 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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31 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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32 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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33 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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34 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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35 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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36 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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37 | * |
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38 | */ |
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39 | |
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40 | #include <stdint.h> |
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41 | #include <stdbool.h> |
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42 | #include <bsp/tms570.h> |
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43 | #include <bsp/tms570-pinmux.h> |
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44 | #include <bsp/tms570_selftest.h> |
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45 | #include <bsp/tms570_hwinit.h> |
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46 | |
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47 | /** |
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48 | * @brief Setup all system PLLs (HCG:setupPLL) |
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49 | * |
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50 | */ |
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51 | void tms570_pll_init( void ) |
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52 | { |
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53 | uint32_t pll12_dis = 0x42; |
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54 | |
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55 | /* Disable PLL1 and PLL2 */ |
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56 | TMS570_SYS1.CSDISSET = pll12_dis; |
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57 | |
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58 | /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ |
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59 | while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { |
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60 | /* Wait */ |
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61 | } |
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62 | |
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63 | /* Clear Global Status Register */ |
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64 | TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP | |
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65 | TMS570_SYS1_GLBSTAT_RFSLIP | |
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66 | TMS570_SYS1_GLBSTAT_OSCFAIL; |
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67 | /** - Configure PLL control registers */ |
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68 | /** @b Initialize @b Pll1: */ |
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69 | |
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70 | /* Setup pll control register 1 */ |
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71 | TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 | |
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72 | TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) | |
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73 | TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */ |
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74 | TMS570_SYS1_PLLCTL1_ROF * 0 | |
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75 | TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) | |
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76 | TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 ); |
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77 | |
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78 | /* Setup pll control register 2 */ |
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79 | TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 | |
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80 | TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) | |
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81 | TMS570_SYS1_PLLCTL2_MULMOD( 7 ) | |
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82 | TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) | |
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83 | TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 ); |
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84 | |
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85 | /** @b Initialize @b Pll2: */ |
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86 | |
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87 | /* Setup pll2 control register */ |
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88 | TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) | |
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89 | TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */ |
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90 | TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) | |
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91 | TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 ); |
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92 | |
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93 | /** - Enable PLL(s) to start up or Lock */ |
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94 | TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */ |
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95 | 0x00000000 | /* CLKSR1 on */ |
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96 | 0x00000008 | /* CLKSR3 off */ |
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97 | 0x00000000 | /* CLKSR4 on */ |
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98 | 0x00000000 | /* CLKSR5 on */ |
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99 | 0x00000000 | /* CLKSR6 on */ |
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100 | 0x00000080; /* CLKSR7 off */ |
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101 | } |
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102 | |
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103 | /** |
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104 | * @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO) |
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105 | * |
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106 | */ |
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107 | /* SourceId : SYSTEM_SourceId_002 */ |
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108 | /* DesignId : SYSTEM_DesignId_002 */ |
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109 | /* Requirements : HL_SR468 */ |
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110 | void tms570_trim_lpo_init( void ) |
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111 | { |
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112 | /** @b Initialize Lpo: */ |
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113 | /** Load TRIM values from OTP if present else load user defined values */ |
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114 | /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ |
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115 | TMS570_SYS1.LPOMONCTL = TMS570_SYS1_LPOMONCTL_BIAS_ENABLE | |
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116 | TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT * 0 | |
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117 | TMS570_SYS1_LPOMONCTL_HFTRIM( 16 ) | |
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118 | 16; /* LFTRIM */ |
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119 | } |
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120 | |
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121 | /* FIXME */ |
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122 | enum tms570_flash_power_modes { |
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123 | TMS570_FLASH_SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ |
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124 | TMS570_FLASH_SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ |
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125 | TMS570_FLASH_SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ |
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126 | }; |
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127 | |
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128 | enum tms570_system_clock_source { |
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129 | TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ |
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130 | TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ |
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131 | TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ |
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132 | TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ |
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133 | TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ |
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134 | TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ |
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135 | TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ |
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136 | TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ |
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137 | }; |
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138 | |
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139 | /** |
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140 | * @brief Setup Flash memory parameters and timing (HCG:setupFlash) |
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141 | * |
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142 | */ |
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143 | /* SourceId : SYSTEM_SourceId_003 */ |
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144 | /* DesignId : SYSTEM_DesignId_003 */ |
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145 | /* Requirements : HL_SR457 */ |
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146 | void tms570_flash_init( void ) |
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147 | { |
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148 | /** - Setup flash read mode, address wait states and data wait states */ |
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149 | TMS570_FLASH.FRDCNTL = TMS570_FLASH_FRDCNTL_RWAIT( 3 ) | |
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150 | TMS570_FLASH_FRDCNTL_ASWSTEN | |
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151 | TMS570_FLASH_FRDCNTL_ENPIPE; |
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152 | |
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153 | /** - Setup flash access wait states for bank 7 */ |
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154 | TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0x5 ); |
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155 | TMS570_FLASH.EEPROMCONFIG = TMS570_FLASH_EEPROMCONFIG_EWAIT( 3 ) | |
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156 | TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN * 0 | |
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157 | TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE( 2 ); |
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158 | |
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159 | /** - Disable write access to flash state machine registers */ |
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160 | TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0xA ); |
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161 | |
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162 | /** - Setup flash bank power modes */ |
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163 | TMS570_FLASH.FBFALLBACK = TMS570_FLASH_FBFALLBACK_BANKPWR7( |
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164 | TMS570_FLASH_SYS_ACTIVE ) | |
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165 | TMS570_FLASH_FBFALLBACK_BANKPWR1( |
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166 | TMS570_FLASH_SYS_ACTIVE ) | |
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167 | TMS570_FLASH_FBFALLBACK_BANKPWR0( |
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168 | TMS570_FLASH_SYS_ACTIVE ); |
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169 | } |
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170 | |
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171 | /** |
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172 | * @brief Power-up all peripherals and enable their clocks (HCG:periphInit) |
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173 | * |
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174 | */ |
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175 | /* SourceId : SYSTEM_SourceId_004 */ |
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176 | /* DesignId : SYSTEM_DesignId_004 */ |
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177 | /* Requirements : HL_SR470 */ |
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178 | void tms570_periph_init( void ) |
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179 | { |
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180 | /** - Disable Peripherals before peripheral powerup*/ |
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181 | TMS570_SYS1.CLKCNTL &= ~TMS570_SYS1_CLKCNTL_PENA; |
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182 | |
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183 | /** - Release peripherals from reset and enable clocks to all peripherals */ |
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184 | /** - Power-up all peripherals */ |
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185 | TMS570_PCR.PSPWRDWNCLR0 = 0xFFFFFFFFU; |
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186 | TMS570_PCR.PSPWRDWNCLR1 = 0xFFFFFFFFU; |
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187 | TMS570_PCR.PSPWRDWNCLR2 = 0xFFFFFFFFU; |
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188 | TMS570_PCR.PSPWRDWNCLR3 = 0xFFFFFFFFU; |
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189 | |
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190 | /** - Enable Peripherals */ |
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191 | TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA; |
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192 | } |
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193 | |
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194 | /** |
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195 | * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks) |
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196 | * |
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197 | */ |
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198 | /* SourceId : SYSTEM_SourceId_005 */ |
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199 | /* DesignId : SYSTEM_DesignId_005 */ |
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200 | /* Requirements : HL_SR469 */ |
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201 | void tms570_map_clock_init( void ) |
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202 | { |
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203 | uint32_t sys_csvstat, sys_csdis; |
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204 | |
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205 | /** @b Initialize @b Clock @b Tree: */ |
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206 | /** - Disable / Enable clock domain */ |
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207 | TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */ |
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208 | ( 0U << 5U ) | /* AVCLK 2 OFF */ |
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209 | ( 0U << 8U ) | /* VCLK3 OFF */ |
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210 | ( 0U << 9U ) | /* VCLK4 OFF */ |
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211 | ( 1U << 10U ) | /* AVCLK 3 OFF */ |
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212 | ( 0U << 11U ); /* AVCLK 4 OFF */ |
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213 | |
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214 | /* Work Around for Errata SYS#46: |
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215 | * |
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216 | * Errata Description: |
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217 | * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid |
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218 | * Workaround: |
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219 | * Always check the CSDIS register to make sure the clock source is turned on and check |
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220 | * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. |
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221 | */ |
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222 | /** - Wait for until clocks are locked */ |
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223 | sys_csvstat = TMS570_SYS1.CSVSTAT; |
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224 | sys_csdis = TMS570_SYS1.CSDIS; |
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225 | |
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226 | while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != |
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227 | ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { |
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228 | sys_csvstat = TMS570_SYS1.CSVSTAT; |
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229 | sys_csdis = TMS570_SYS1.CSDIS; |
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230 | } /* Wait */ |
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231 | |
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232 | /* Now the PLLs are locked and the PLL outputs can be sped up */ |
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233 | /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ |
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234 | TMS570_SYS1.PLLCTL1 = |
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235 | ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) | |
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236 | TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 ); |
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237 | /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ |
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238 | TMS570_SYS2.PLLCTL3 = |
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239 | ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) | |
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240 | TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 ); |
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241 | |
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242 | /* Enable/Disable Frequency modulation */ |
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243 | TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA; |
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244 | |
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245 | /** - Map device clock domains to desired sources and configure top-level dividers */ |
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246 | /** - All clock domains are working off the default clock sources until now */ |
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247 | /** - The below assignments can be easily modified using the HALCoGen GUI */ |
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248 | |
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249 | /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ |
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250 | TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) | |
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251 | TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) | |
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252 | TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 ); |
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253 | |
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254 | /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ |
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255 | TMS570_SYS1.CLKCNTL = |
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256 | ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) | |
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257 | TMS570_SYS1_CLKCNTL_VCLK2R( 1 ); |
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258 | |
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259 | TMS570_SYS1.CLKCNTL = |
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260 | ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) | |
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261 | TMS570_SYS1_CLKCNTL_VCLKR( 1 ); |
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262 | |
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263 | TMS570_SYS2.CLK2CNTRL = |
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264 | ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) | |
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265 | TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 ); |
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266 | |
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267 | TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) | |
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268 | ( 1U << 8U ); /* FIXME: unknown in manual*/ |
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269 | |
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270 | /** - Setup RTICLK1 and RTICLK2 clocks */ |
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271 | TMS570_SYS1.RCLKSRC = ( 1U << 24U ) | |
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272 | ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */ |
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273 | TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) | |
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274 | TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK ); |
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275 | |
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276 | /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ |
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277 | TMS570_SYS1.VCLKASRC = |
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278 | TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) | |
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279 | TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK ); |
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280 | |
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281 | TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) | |
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282 | TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 | |
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283 | TMS570_SYS2_VCLKACON1_VCLKA4S( |
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284 | TMS570_SYS_CLK_SRC_VCLK ) | |
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285 | TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) | |
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286 | TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 | |
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287 | TMS570_SYS2_VCLKACON1_VCLKA3S( |
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288 | TMS570_SYS_CLK_SRC_VCLK ); |
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289 | } |
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290 | |
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291 | /** |
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292 | * @brief TMS570 system hardware initialization (HCG:systemInit) |
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293 | * |
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294 | */ |
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295 | /* SourceId : SYSTEM_SourceId_006 */ |
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296 | /* DesignId : SYSTEM_DesignId_006 */ |
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297 | /* Requirements : HL_SR471 */ |
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298 | void tms570_system_hw_init( void ) |
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299 | { |
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300 | uint32_t efc_check_status; |
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301 | |
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302 | /* Configure PLL control registers and enable PLLs. |
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303 | * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. |
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304 | * This initialization sequence performs all the tasks that are not |
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305 | * required to be done at full application speed while the PLL locks. |
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306 | */ |
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307 | tms570_pll_init(); |
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308 | |
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309 | /* Run eFuse controller start-up checks and start eFuse controller ECC self-test. |
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310 | * This includes a check for the eFuse controller error outputs to be stuck-at-zero. |
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311 | */ |
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312 | efc_check_status = tms570_efc_check(); |
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313 | |
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314 | /* Enable clocks to peripherals and release peripheral reset */ |
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315 | tms570_periph_init(); |
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316 | |
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317 | /* Configure device-level multiplexing and I/O multiplexing */ |
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318 | tms570_pinmux_init(); |
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319 | |
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320 | /* Enable external memory interface */ |
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321 | TMS570_SYS1.GPREG1 |= TMS570_SYS1_GPREG1_EMIF_FUNC; |
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322 | |
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323 | if ( efc_check_status == 0U ) { |
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324 | /* Wait for eFuse controller self-test to complete and check results */ |
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325 | if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */ |
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326 | bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */ |
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327 | } |
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328 | } else if ( efc_check_status == 2U ) { |
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329 | /* Wait for eFuse controller self-test to complete and check results */ |
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330 | if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */ |
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331 | bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */ |
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332 | } else { |
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333 | bsp_selftest_fail_notification( EFCCHECK_FAIL2 ); |
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334 | } |
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335 | } else { |
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336 | /* Empty */ |
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337 | } |
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338 | |
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339 | /** - Set up flash address and data wait states based on the target CPU clock frequency |
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340 | * The number of address and data wait states for the target CPU clock frequency are specified |
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341 | * in the specific part's datasheet. |
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342 | */ |
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343 | tms570_flash_init(); |
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344 | |
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345 | /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ |
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346 | tms570_trim_lpo_init(); |
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347 | |
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348 | /** - Wait for PLLs to start up and map clock domains to desired clock sources */ |
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349 | tms570_map_clock_init(); |
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350 | |
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351 | /** - set ECLK pins functional mode */ |
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352 | TMS570_SYS1.SYSPC1 = 0U; |
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353 | |
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354 | /** - set ECLK pins default output value */ |
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355 | TMS570_SYS1.SYSPC4 = 0U; |
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356 | |
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357 | /** - set ECLK pins output direction */ |
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358 | TMS570_SYS1.SYSPC2 = 1U; |
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359 | |
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360 | /** - set ECLK pins open drain enable */ |
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361 | TMS570_SYS1.SYSPC7 = 0U; |
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362 | |
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363 | /** - set ECLK pins pullup/pulldown enable */ |
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364 | TMS570_SYS1.SYSPC8 = 0U; |
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365 | |
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366 | /** - set ECLK pins pullup/pulldown select */ |
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367 | TMS570_SYS1.SYSPC9 = 1U; |
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368 | |
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369 | /** - Setup ECLK */ |
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370 | TMS570_SYS1.ECPCNTL = TMS570_SYS1_ECPCNTL_ECPSSEL * 0 | |
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371 | TMS570_SYS1_ECPCNTL_ECPCOS * 0 | |
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372 | TMS570_SYS1_ECPCNTL_ECPDIV( 8 - 1 ); |
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373 | } |
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374 | |
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375 | #if 0 |
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376 | errata_PBIST_4 |
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377 | vimInit |
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378 | #endif |
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