1 | /** |
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2 | * @file init_emif_sdram.c |
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3 | * |
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4 | * @ingroup tms570 |
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5 | * |
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6 | * @brief Initialization of external memory/SDRAM interface. |
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7 | */ |
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8 | |
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9 | #include <stdint.h> |
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10 | #include <bsp/tms570.h> |
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11 | #include "tms570_hwinit.h" |
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12 | |
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13 | void tms570_emif_sdram_init( void ) |
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14 | { |
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15 | uint32_t dummy; |
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16 | uint32_t sdtimr = 0; |
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17 | uint32_t sdcr = 0; |
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18 | |
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19 | /* Do not run attempt to initialize SDRAM when code is running from it */ |
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20 | if ( ( (void*)tms570_emif_sdram_init >= (void*)TMS570_SDRAM_START_PTR ) && |
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21 | ( (void*)tms570_emif_sdram_init <= (void*)TMS570_SDRAM_WINDOW_END_PTR ) ) |
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22 | return; |
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23 | |
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24 | sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 ); |
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25 | sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 ); |
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26 | sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 ); |
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27 | sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 ); |
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28 | sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 ); |
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29 | sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 ); |
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30 | sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 ); |
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31 | |
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32 | TMS570_EMIF.SDTIMR = sdtimr; |
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33 | |
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34 | /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ |
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35 | TMS570_EMIF.SDSRETR = 5; |
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36 | /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ |
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37 | TMS570_EMIF.SDRCR = 2000; |
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38 | |
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39 | /* SR - Self-Refresh mode bit. */ |
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40 | sdcr |= TMS570_EMIF_SDCR_SR * 0; |
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41 | /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */ |
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42 | sdcr |= TMS570_EMIF_SDCR_PD * 0; |
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43 | /* PDWR - Perform refreshes during power down. */ |
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44 | sdcr |= TMS570_EMIF_SDCR_PDWR * 0; |
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45 | /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */ |
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46 | sdcr |= TMS570_EMIF_SDCR_NM * 1; |
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47 | /* CL - CAS Latency. */ |
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48 | sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 ); |
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49 | /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ |
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50 | sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1; |
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51 | /* IBANK - Internal SDRAM Bank size. */ |
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52 | sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */ |
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53 | /* Page Size. This field defines the internal page size of connected SDRAM devices. */ |
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54 | sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */ |
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55 | |
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56 | TMS570_EMIF.SDCR = sdcr; |
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57 | |
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58 | dummy = *(volatile uint32_t*)TMS570_SDRAM_START_PTR; |
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59 | (void) dummy; |
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60 | TMS570_EMIF.SDRCR = 31; |
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61 | |
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62 | /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ |
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63 | TMS570_EMIF.SDRCR = 312; |
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64 | } |
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