source: rtems/bsps/arm/tms570/start/init_emif_sdram.c @ 350b07a0

5
Last change on this file since 350b07a0 was a62c75c1, checked in by Sebastian Huber <sebastian.huber@…>, on 04/22/18 at 13:38:55

bsp/tms570: Move more start to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/**
2 * @file init_emif_sdram.c
3 *
4 * @ingroup tms570
5 *
6 * @brief Initialization of external memory/SDRAM interface.
7 */
8
9#include <stdint.h>
10#include <bsp/tms570.h>
11#include "tms570_hwinit.h"
12
13void tms570_emif_sdram_init( void )
14{
15  uint32_t dummy;
16  uint32_t sdtimr = 0;
17  uint32_t sdcr = 0;
18
19  /* Do not run attempt to initialize SDRAM when code is running from it */
20  if ( ( (void*)tms570_emif_sdram_init >= (void*)TMS570_SDRAM_START_PTR ) &&
21       ( (void*)tms570_emif_sdram_init <= (void*)TMS570_SDRAM_WINDOW_END_PTR ) )
22    return;
23
24  sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 );
25  sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 );
26  sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 );
27  sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 );
28  sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 );
29  sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 );
30  sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 );
31
32  TMS570_EMIF.SDTIMR = sdtimr;
33
34  /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
35  TMS570_EMIF.SDSRETR = 5;
36  /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
37  TMS570_EMIF.SDRCR = 2000;
38
39  /* SR - Self-Refresh mode bit. */
40  sdcr |= TMS570_EMIF_SDCR_SR * 0;
41  /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */
42  sdcr |= TMS570_EMIF_SDCR_PD * 0;
43  /* PDWR - Perform refreshes during power down. */
44  sdcr |= TMS570_EMIF_SDCR_PDWR * 0;
45  /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */
46  sdcr |= TMS570_EMIF_SDCR_NM * 1;
47  /* CL - CAS Latency. */
48  sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 );
49  /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
50  sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1;
51  /* IBANK - Internal SDRAM Bank size. */
52  sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */
53  /* Page Size. This field defines the internal page size of connected SDRAM devices. */
54  sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */
55
56  TMS570_EMIF.SDCR = sdcr;
57
58  dummy = *(volatile uint32_t*)TMS570_SDRAM_START_PTR;
59  (void) dummy;
60  TMS570_EMIF.SDRCR = 31;
61
62  /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
63  TMS570_EMIF.SDRCR = 312;
64}
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