1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsARMTMS570 |
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5 | * |
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6 | * @brief TMS570 interrupt support functions definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> |
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11 | * |
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12 | * Google Summer of Code 2014 at |
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13 | * Czech Technical University in Prague |
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14 | * Zikova 1903/4 |
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15 | * 166 36 Praha 6 |
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16 | * Czech Republic |
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17 | * |
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18 | * Based on LPC24xx and LPC1768 BSP |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #include <bsp.h> |
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26 | #include <bsp/irq-generic.h> |
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27 | #include <bsp/tms570-vim.h> |
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28 | #include <bsp/irq.h> |
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29 | #include <rtems/score/armv4.h> |
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30 | |
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31 | unsigned int priorityTable[BSP_INTERRUPT_VECTOR_COUNT]; |
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32 | |
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33 | /** |
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34 | * @brief Set priority of the interrupt vector. |
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35 | * |
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36 | * This function is here because of compability. It should set |
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37 | * priority of the interrupt vector. |
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38 | * @warning It does not set any priority at HW layer. It is nearly imposible to |
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39 | * @warning set priority of the interrupt on TMS570 in a nice way. |
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40 | * @param[in] vector vector of isr |
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41 | * @param[in] priority new priority assigned to the vector |
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42 | * @return Void |
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43 | */ |
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44 | void tms570_irq_set_priority( |
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45 | rtems_vector_number vector, |
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46 | unsigned priority |
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47 | ) |
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48 | { |
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49 | if ( bsp_interrupt_is_valid_vector(vector) ) { |
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50 | priorityTable[vector] = priority; |
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51 | } |
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52 | } |
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53 | |
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54 | /** |
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55 | * @brief Gets priority of the interrupt vector. |
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56 | * |
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57 | * This function is here because of compability. It returns priority |
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58 | * of the isr vector last set by tms570_irq_set_priority function. |
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59 | * |
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60 | * @warning It does not return any real priority of the HW layer. |
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61 | * @param[in] vector vector of isr |
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62 | * @retval 0 vector is invalid. |
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63 | * @retval priority priority of the interrupt |
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64 | */ |
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65 | unsigned tms570_irq_get_priority( |
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66 | rtems_vector_number vector |
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67 | ) |
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68 | { |
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69 | if ( bsp_interrupt_is_valid_vector(vector) ) { |
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70 | return priorityTable[vector]; |
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71 | } |
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72 | return 0; |
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73 | } |
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74 | |
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75 | /** |
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76 | * @brief Interrupt dispatch |
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77 | * |
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78 | * Called by OS to determine which interrupt occured. |
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79 | * Function passes control to interrupt handler. |
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80 | * |
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81 | * @return Void |
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82 | */ |
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83 | void bsp_interrupt_dispatch(void) |
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84 | { |
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85 | rtems_vector_number vector = TMS570_VIM.IRQINDEX-1; |
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86 | |
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87 | bsp_interrupt_handler_dispatch(vector); |
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88 | } |
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89 | |
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90 | /** |
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91 | * @brief enables interrupt vector in the HW |
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92 | * |
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93 | * Enables HW interrupt for specified vector |
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94 | * |
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95 | * @param[in] vector vector of the isr which needs to be enabled. |
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96 | * @retval RTEMS_INVALID_ID vector is invalid. |
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97 | * @retval RTEMS_SUCCESSFUL interrupt source enabled. |
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98 | */ |
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99 | rtems_status_code bsp_interrupt_get_attributes( |
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100 | rtems_vector_number vector, |
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101 | rtems_interrupt_attributes *attributes |
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102 | ) |
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103 | { |
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104 | return RTEMS_SUCCESSFUL; |
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105 | } |
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106 | |
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107 | rtems_status_code bsp_interrupt_is_pending( |
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108 | rtems_vector_number vector, |
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109 | bool *pending |
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110 | ) |
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111 | { |
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112 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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113 | bsp_interrupt_assert(pending != NULL); |
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114 | *pending = false; |
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115 | return RTEMS_UNSATISFIED; |
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116 | } |
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117 | |
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118 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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119 | { |
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120 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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121 | return RTEMS_UNSATISFIED; |
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122 | } |
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123 | |
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124 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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125 | { |
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126 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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127 | return RTEMS_UNSATISFIED; |
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128 | } |
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129 | |
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130 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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131 | rtems_vector_number vector, |
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132 | bool *enabled |
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133 | ) |
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134 | { |
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135 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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136 | bsp_interrupt_assert(enabled != NULL); |
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137 | *enabled = false; |
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138 | return RTEMS_UNSATISFIED; |
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139 | } |
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140 | |
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141 | rtems_status_code bsp_interrupt_vector_enable( |
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142 | rtems_vector_number vector |
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143 | ) |
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144 | { |
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145 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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146 | TMS570_VIM.REQENASET[vector >> 5] = 1 << (vector & 0x1f); |
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147 | return RTEMS_SUCCESSFUL; |
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148 | } |
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149 | |
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150 | /** |
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151 | * @brief disables interrupt vector in the HW |
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152 | * |
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153 | * Disables HW interrupt for specified vector |
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154 | * |
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155 | * @param[in] vector vector of the isr which needs to be disabled. |
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156 | * @retval RTEMS_INVALID_ID vector is invalid. |
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157 | * @retval RTEMS_SUCCESSFUL interrupt source disabled. |
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158 | */ |
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159 | rtems_status_code bsp_interrupt_vector_disable( |
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160 | rtems_vector_number vector |
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161 | ) |
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162 | { |
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163 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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164 | TMS570_VIM.REQENACLR[vector >> 5] = 1 << (vector & 0x1f); |
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165 | return RTEMS_SUCCESSFUL; |
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166 | } |
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167 | |
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168 | /** |
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169 | * @brief Init function of interrupt module |
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170 | * |
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171 | * Resets vectored interrupt interface to default state. |
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172 | * Disables all interrupts. |
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173 | * Set all sources as IRQ (not FIR). |
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174 | * |
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175 | * @retval RTEMS_SUCCESSFUL All is set |
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176 | */ |
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177 | void bsp_interrupt_facility_initialize(void) |
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178 | { |
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179 | void (**vim_vec)(void) = (void (**)(void)) 0xFFF82000; |
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180 | unsigned int value = 0x00010203; |
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181 | unsigned int i = 0; |
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182 | uint32_t sctlr; |
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183 | |
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184 | /* Disable interrupts */ |
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185 | for ( i = 0; i < 3; i++ ) { |
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186 | TMS570_VIM.REQENACLR[i] = 0xffffffff; |
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187 | } |
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188 | /* Map default events on interrupt vectors */ |
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189 | for ( i = 0; i < 24; i += 1, value += 0x04040404) { |
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190 | TMS570_VIM.CHANCTRL[i] = value; |
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191 | } |
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192 | /* Set all vectors as IRQ (not FIR) */ |
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193 | TMS570_VIM.FIRQPR[0] = 3; |
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194 | TMS570_VIM.FIRQPR[1] = 0; |
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195 | TMS570_VIM.FIRQPR[2] = 0; |
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196 | |
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197 | /* |
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198 | _CPU_ISR_install_vector( |
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199 | ARM_EXCEPTION_IRQ, |
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200 | _ARMV4_Exception_interrupt, |
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201 | NULL |
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202 | ); |
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203 | |
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204 | Call to setup of interrupt entry in CPU level exception vectors table |
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205 | is not used (necessary/possible) because the table is provided |
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206 | by c/src/lib/libbsp/arm/shared/start/start.S and POM overlay |
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207 | solution remaps that to address zero. |
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208 | */ |
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209 | |
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210 | for ( i = 0; i <= 94; ++i ) { |
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211 | vim_vec[i] = _ARMV4_Exception_interrupt; |
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212 | } |
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213 | /* Clear bit VE in SCTLR register to not use VIM IRQ exception bypass*/ |
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214 | asm volatile ("mrc p15, 0, %0, c1, c0, 0\n": "=r" (sctlr)); |
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215 | /* |
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216 | * Disable bypass of CPU level exception table for interrupt entry which |
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217 | * can be provided by VIM hardware |
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218 | */ |
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219 | sctlr &= ~(1 << 24); |
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220 | #if 0 |
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221 | /* |
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222 | * Option to enable exception table bypass for interrupts |
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223 | * |
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224 | * Because RTEMS requires all interrupts to be serviced through |
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225 | * common _ARMV4_Exception_interrupt handler to allow task switching |
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226 | * on exit from interrupt working correctly, vim_vec cannot point |
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227 | * directly to individual vector handlers and need to point |
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228 | * to single entry path. But if TMS570_VIM.IRQINDEX is then used |
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229 | * to target execution to corresponding service then for some |
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230 | * peripherals (i.e. EMAC) interrupt is already acknowledged |
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231 | * by VIM and IRQINDEX is read as zero which leads to spurious |
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232 | * interrupt and peripheral not serviced/blocked. |
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233 | * |
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234 | * To analyze this behavior we used trampolines which setup |
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235 | * bsp_interrupt_vector_inject and pass execution to |
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236 | * _ARMV4_Exception_interrupt. It works but is more ugly than |
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237 | * use of POM remap for these cases where application does not |
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238 | * start at address 0x00000000. If RTEMS image is placed at |
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239 | * memory space beginning then no of these constructs is necessary. |
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240 | */ |
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241 | sctlr |= 1 << 24; |
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242 | #endif |
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243 | asm volatile ("mcr p15, 0, %0, c1, c0, 0\n": : "r" (sctlr)); |
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244 | } |
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