1 | /* The header file is generated by make_header.py from TCRAM.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_TMS570_TCRAM |
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40 | #define LIBBSP_ARM_TMS570_TCRAM |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t RAMCTRL; /*TCRAM Module Control Register*/ |
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46 | uint32_t RAMTHRESHOLD; /*TCRAM Module Single-Bit Error Correction Threshold Register*/ |
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47 | uint32_t RAMOCCUR; /*TCRAM Module Single-Bit Error Occurrences Control Register*/ |
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48 | uint32_t RAMINTCTRL; /*TCRAM Module Interrupt Control Register*/ |
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49 | uint32_t RAMERRSTATUS; /*TCRAM Module Error Status Register*/ |
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50 | uint32_t RAMSERRADDR; /*TCRAM Module Single-Bit Error Address Register*/ |
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51 | uint8_t reserved1 [4]; |
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52 | uint32_t RAMUERRADDR; /*TCRAM Module Uncorrectable Error Address Register*/ |
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53 | uint8_t reserved2 [16]; |
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54 | uint32_t RAMTEST; /*TCRAM Module Test Mode Control Register*/ |
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55 | uint8_t reserved3 [4]; |
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56 | uint32_t RAMADDRDECVECT; /*TCRAM Module Test Mode Vector Register*/ |
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57 | uint32_t RAMPERADDR; /*TCRAM Module Parity Error Address Register*/ |
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58 | } tms570_tcram_t; |
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59 | |
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60 | |
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61 | /*--------------------TMS570_TCRAM_RAMCTRL--------------------*/ |
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62 | /* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */ |
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63 | #define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30) |
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64 | |
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65 | /* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */ |
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66 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27) |
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67 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27) |
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68 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
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69 | |
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70 | /* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */ |
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71 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19) |
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72 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19) |
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73 | #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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74 | |
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75 | /* field: ECC_WR_EN - ECC Memory Write Enable. */ |
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76 | #define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8) |
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77 | |
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78 | /* field: ECC_DETECT_EN - ECC Detect Enable. */ |
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79 | #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3) |
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80 | #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3) |
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81 | #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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82 | |
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83 | |
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84 | /*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/ |
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85 | /* field: THRESHOLD - Single-bit Error Threshold Count. */ |
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86 | #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15) |
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87 | #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15) |
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88 | #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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89 | |
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90 | |
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91 | /*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/ |
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92 | /* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */ |
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93 | #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15) |
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94 | #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15) |
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95 | #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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96 | |
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97 | |
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98 | /*------------------TMS570_TCRAM_RAMINTCTRL------------------*/ |
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99 | /* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */ |
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100 | #define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0) |
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101 | |
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102 | |
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103 | /*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/ |
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104 | /* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */ |
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105 | #define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9) |
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106 | |
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107 | /* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */ |
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108 | #define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8) |
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109 | |
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110 | /* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */ |
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111 | #define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5) |
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112 | |
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113 | /* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */ |
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114 | #define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4) |
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115 | |
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116 | /* field: ADDR_DEC_FAIL - Address decode failed. */ |
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117 | #define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2) |
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118 | |
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119 | /* field: SERR - Single Error Status. */ |
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120 | #define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0) |
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121 | |
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122 | |
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123 | /*------------------TMS570_TCRAM_RAMSERRADDR------------------*/ |
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124 | /* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */ |
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125 | #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17) |
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126 | #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17) |
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127 | #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17) |
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128 | |
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129 | |
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130 | /*------------------TMS570_TCRAM_RAMUERRADDR------------------*/ |
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131 | /* field: UNCORRECTABLE - address parity error. */ |
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132 | #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22) |
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133 | #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22) |
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134 | #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) |
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135 | |
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136 | |
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137 | /*--------------------TMS570_TCRAM_RAMTEST--------------------*/ |
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138 | /* field: TRIGGER - Test Trigger. */ |
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139 | #define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8) |
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140 | |
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141 | /* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */ |
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142 | #define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7) |
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143 | #define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7) |
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144 | #define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7) |
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145 | |
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146 | /* field: TEST_ENABLE - Test Enable. */ |
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147 | #define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3) |
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148 | #define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3) |
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149 | #define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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150 | |
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151 | |
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152 | /*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/ |
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153 | /* field: ECC_SELECT - ECC Select. */ |
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154 | #define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26) |
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155 | |
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156 | /* field: RAM_CHIP_SELECT - RAM Chip Select. */ |
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157 | #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15) |
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158 | #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15) |
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159 | #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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160 | |
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161 | |
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162 | /*------------------TMS570_TCRAM_RAMPERADDR------------------*/ |
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163 | /* field: ADDRESS_PARITY - Parity Error Address. */ |
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164 | #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22) |
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165 | #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22) |
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166 | #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22) |
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167 | |
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168 | |
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169 | |
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170 | #endif /* LIBBSP_ARM_TMS570_TCRAM */ |
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