source: rtems/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 8.1 KB
Line 
1/* The header file is generated by make_header.py from TCRAM.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_TCRAM
40#define LIBBSP_ARM_TMS570_TCRAM
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t RAMCTRL;           /*TCRAM Module Control Register*/
46  uint32_t RAMTHRESHOLD;      /*TCRAM Module Single-Bit Error Correction Threshold Register*/
47  uint32_t RAMOCCUR;          /*TCRAM Module Single-Bit Error Occurrences Control Register*/
48  uint32_t RAMINTCTRL;        /*TCRAM Module Interrupt Control Register*/
49  uint32_t RAMERRSTATUS;      /*TCRAM Module Error Status Register*/
50  uint32_t RAMSERRADDR;       /*TCRAM Module Single-Bit Error Address Register*/
51  uint8_t reserved1 [4];
52  uint32_t RAMUERRADDR;       /*TCRAM Module Uncorrectable Error Address Register*/
53  uint8_t reserved2 [16];
54  uint32_t RAMTEST;           /*TCRAM Module Test Mode Control Register*/
55  uint8_t reserved3 [4];
56  uint32_t RAMADDRDECVECT;    /*TCRAM Module Test Mode Vector Register*/
57  uint32_t RAMPERADDR;        /*TCRAM Module Parity Error Address Register*/
58} tms570_tcram_t;
59
60
61/*--------------------TMS570_TCRAM_RAMCTRL--------------------*/
62/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
63#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30)
64
65/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
66#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
67#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27)
68#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
69
70/* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */
71#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19)
72#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19)
73#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
74
75/* field: ECC_WR_EN - ECC Memory Write Enable. */
76#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8)
77
78/* field: ECC_DETECT_EN - ECC Detect Enable. */
79#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
80#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3)
81#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
82
83
84/*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/
85/* field: THRESHOLD - Single-bit Error Threshold Count. */
86#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
87#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
88#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
89
90
91/*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/
92/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
93#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
94#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
95#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
96
97
98/*------------------TMS570_TCRAM_RAMINTCTRL------------------*/
99/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
100#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0)
101
102
103/*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/
104/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
105#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9)
106
107/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
108#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8)
109
110/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
111#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5)
112
113/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
114#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4)
115
116/* field: ADDR_DEC_FAIL - Address decode failed. */
117#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2)
118
119/* field: SERR - Single Error Status. */
120#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0)
121
122
123/*------------------TMS570_TCRAM_RAMSERRADDR------------------*/
124/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
125#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
126#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
127#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
128
129
130/*------------------TMS570_TCRAM_RAMUERRADDR------------------*/
131/* field: UNCORRECTABLE - address parity error. */
132#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
133#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
134#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
135
136
137/*--------------------TMS570_TCRAM_RAMTEST--------------------*/
138/* field: TRIGGER - Test Trigger. */
139#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8)
140
141/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
142#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
143#define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7)
144#define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
145
146/* field: TEST_ENABLE - Test Enable. */
147#define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3)
148#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3)
149#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
150
151
152/*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/
153/* field: ECC_SELECT - ECC Select. */
154#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26)
155
156/* field: RAM_CHIP_SELECT - RAM Chip Select. */
157#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
158#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15)
159#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
160
161
162/*------------------TMS570_TCRAM_RAMPERADDR------------------*/
163/* field: ADDRESS_PARITY - Parity Error Address. */
164#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
165#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
166#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
167
168
169
170#endif /* LIBBSP_ARM_TMS570_TCRAM */
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