source: rtems/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 18.7 KB
Line 
1/* The header file is generated by make_header.py from SCI.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_SCI
40#define LIBBSP_ARM_TMS570_SCI
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t GCR0;              /*SCI Global Control Register 0*/
46  uint32_t GCR1;              /*SCI Global Control Register 1*/
47  uint32_t GCR2;              /*SCI Global Control Register 2*/
48  uint32_t SETINT;            /*SCI Set Interrupt Register*/
49  uint32_t CLEARINT;          /*SCI Clear Interrupt Register*/
50  uint32_t SETINTLVL;         /*SCI Set Interrupt Level Register*/
51  uint32_t CLEARINTLVL;       /*SCI Clear Interrupt Level Register*/
52  uint32_t FLR;               /*SCI Flags Register*/
53  uint32_t INTVECT0;          /*SCI Interrupt Vector Offset 0*/
54  uint32_t INTVECT1;          /*SCI Interrupt Vector Offset 1*/
55  uint32_t FORMAT;            /*SCI Format Control Register*/
56  uint32_t BRS;               /*Baud Rate Selection Register*/
57  uint32_t ED;                /*Receiver Emulation Data Buffer*/
58  uint32_t RD;                /*Receiver Data Buffer*/
59  uint32_t TD;                /*Transmit Data Buffer*/
60  uint32_t PIO0;              /*SCI Pin I/O Control Register 0*/
61  uint32_t PIO1;              /*SCI Pin I/O Control Register 1*/
62  uint32_t PIO2;              /*SCI Pin I/O Control Register 2*/
63  uint32_t PIO3;              /*SCI Pin I/O Control Register 3*/
64  uint32_t PIO4;              /*SCI Pin I/O Control Register 4*/
65  uint32_t PIO5;              /*SCI Pin I/O Control Register 5*/
66  uint32_t PIO6;              /*SCI Pin I/O Control Register 6*/
67  uint32_t PIO7;              /*SCI Pin I/O Control Register 7*/
68  uint32_t PIO8;              /*SCI Pin I/O Control Register 8*/
69  uint8_t reserved1 [48];
70  uint32_t IODFTCTRL;         /*Input/Output Error Enable Register*/
71} tms570_sci_t;
72
73
74/*----------------------TMS570_SCI_GCR0----------------------*/
75/* field: Reserved - Read returns 0. Writes have no effect. */
76#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
77#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
78#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
79
80/* field: RESET - This bit resets the SCI module. */
81#define TMS570_SCI_GCR0_RESET BSP_BIT32(0)
82
83
84/*----------------------TMS570_SCI_GCR1----------------------*/
85/* field: TXENA - Transmit enable. */
86#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25)
87
88/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
89#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24)
90
91/* field: CONT - Continue on suspend. */
92#define TMS570_SCI_GCR1_CONT BSP_BIT32(17)
93
94/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
95#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16)
96
97/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
98#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9)
99
100/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
101#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8)
102
103/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
104#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7)
105
106/* field: CLOCK - CLOCK */
107#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5)
108
109/* field: STOP - SCI number of stop bits per frame. */
110#define TMS570_SCI_GCR1_STOP BSP_BIT32(4)
111
112/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
113#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3)
114
115/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
116#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2)
117
118/* field: TIMING_MODE - SCI timing mode bit. */
119#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1)
120
121/* field: COMM_MODE - SCI communication mode bit. */
122#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0)
123
124
125/*----------------------TMS570_SCI_GCR2----------------------*/
126/* field: CC - Compare checksum. LIN mode only. */
127#define TMS570_SCI_GCR2_CC BSP_BIT32(17)
128
129/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
130#define TMS570_SCI_GCR2_SC BSP_BIT32(16)
131
132/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
133#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8)
134
135/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
136#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0)
137
138
139/*---------------------TMS570_SCI_SETINT---------------------*/
140/* field: SET_FE_INT -  */
141#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26)
142
143/* field: SET_OE_INT - SET OE INT */
144#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25)
145
146/* field: SET_PE_INT - Set parity interrupt. */
147#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24)
148
149/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
150#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
151
152/* field: SET_RX_DMA - SET RX DMA */
153#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17)
154
155/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
156#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16)
157
158/* field: SET_RX_INT - SET RX INT */
159#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9)
160
161/* field: SET_TX_INT - Set transmitter interrupt. */
162#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8)
163
164/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
165#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
166
167/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
168#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0)
169
170
171/*--------------------TMS570_SCI_CLEARINT--------------------*/
172/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
173#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26)
174
175/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
176#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25)
177
178/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
179#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24)
180
181/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
182#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
183
184/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
185#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
186
187/* field: CLR_TX_DMA - CLR TX DMA */
188#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
189
190/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
191#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9)
192
193/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
194#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8)
195
196/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
197#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
198
199/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
200#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
201
202
203/*--------------------TMS570_SCI_SETINTLVL--------------------*/
204/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
205#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
206
207/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
208#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
209
210/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
211#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
212
213/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
214#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
215
216/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
217#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
218
219/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
220#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
221
222/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
223#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
224
225/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
226#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
227
228
229/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/
230/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
231#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
232
233/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
234#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
235
236/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
237#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
238
239/* field: CLR_PE_INT_LVL -  */
240#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
241
242/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
243#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
244
245/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
246#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
247
248/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
249#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8)
250
251/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
252#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
253
254/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
255#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
256
257
258/*-----------------------TMS570_SCI_FLR-----------------------*/
259/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
260#define TMS570_SCI_FLR_FE BSP_BIT32(26)
261
262/* field: OE - Overrun error flag. */
263#define TMS570_SCI_FLR_OE BSP_BIT32(25)
264
265/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
266#define TMS570_SCI_FLR_PE BSP_BIT32(24)
267
268/* field: RXWAKE - Receiver wakeup detect flag. */
269#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12)
270
271/* field: TX_EMPTY - Transmitter empty flag. */
272#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11)
273
274/* field: TXWAKE - Transmitter wakeup method select. */
275#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10)
276
277/* field: RXRDY - Receiver ready flag. */
278#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9)
279
280/* field: TXRDY - Transmitter buffer register ready flag. */
281#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8)
282
283/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
284#define TMS570_SCI_FLR_BUSY BSP_BIT32(3)
285
286/* field: IDLE - SCI receiver in idle state. */
287#define TMS570_SCI_FLR_IDLE BSP_BIT32(2)
288
289/* field: WAKEUP - Wakeup flag. */
290#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1)
291
292/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
293#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0)
294
295
296/*--------------------TMS570_SCI_INTVECT0--------------------*/
297/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
298#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
299#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
300#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
301
302
303/*--------------------TMS570_SCI_INTVECT1--------------------*/
304/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
305#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
306#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
307#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
308
309
310/*---------------------TMS570_SCI_FORMAT---------------------*/
311/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
312#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
313#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
314#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
315
316
317/*-----------------------TMS570_SCI_BRS-----------------------*/
318/* field: BAUD - SCI 24-bit baud selection. */
319#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
320#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
321#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
322
323
324/*-----------------------TMS570_SCI_ED-----------------------*/
325/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
326#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
327#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
328#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
329
330
331/*-----------------------TMS570_SCI_RD-----------------------*/
332/* field: RD - Receiver data. */
333#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
334#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
335#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
336
337
338/*-----------------------TMS570_SCI_TD-----------------------*/
339/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
340#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
341#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
342#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
343
344
345/*----------------------TMS570_SCI_PIO0----------------------*/
346/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
347#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2)
348
349/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
350#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1)
351
352
353/*----------------------TMS570_SCI_PIO1----------------------*/
354/* field: TX_DIR - Transmit pin direction. */
355#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2)
356
357/* field: RX_DIR - Receive pin direction. */
358#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1)
359
360
361/*----------------------TMS570_SCI_PIO2----------------------*/
362/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
363#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2)
364
365/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
366#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1)
367
368
369/*----------------------TMS570_SCI_PIO3----------------------*/
370/* field: TX_OUT - Transmit pin out. */
371#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2)
372
373/* field: RX_OUT - Receive pin out. */
374#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1)
375
376
377/*----------------------TMS570_SCI_PIO4----------------------*/
378/* field: TX_SET - Transmit pin set. */
379#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2)
380
381/* field: RX_SET - Receive pin set. */
382#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1)
383
384
385/*----------------------TMS570_SCI_PIO5----------------------*/
386/* field: TX_CLR - Transmit pin clear. */
387#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2)
388
389/* field: RX_CLR - Receive pin clear. */
390#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1)
391
392
393/*----------------------TMS570_SCI_PIO6----------------------*/
394/* field: TX_PDR - Transmit pin open drain enable. */
395#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2)
396
397/* field: RX_PDR - Receive pin open drain enable. */
398#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1)
399
400
401/*----------------------TMS570_SCI_PIO7----------------------*/
402/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
403#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2)
404
405/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
406#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1)
407
408
409/*----------------------TMS570_SCI_PIO8----------------------*/
410/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
411#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2)
412
413/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
414#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1)
415
416
417/*--------------------TMS570_SCI_IODFTCTRL--------------------*/
418/* field: FEN - Frame error enable. This bit is used to create a frame error. */
419#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26)
420
421/* field: PEN - Parity error enable. This bit is used to create a parity error. */
422#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25)
423
424/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
425#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
426
427/* field: PIN_SAMPLE_MASK - Pin sample mask. */
428#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
429#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20)
430#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20)
431
432/* field: TX_SHIFT - Transmit shift. */
433#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18)
434#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18)
435#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
436
437/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */
438#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11)
439#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
440#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
441
442/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
443#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1)
444
445/* field: RXPENA - Module analog loopback through receive pin enable. */
446#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0)
447
448
449
450#endif /* LIBBSP_ARM_TMS570_SCI */
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