1 | /* The header file is generated by make_header.py from RTI.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_TMS570_RTI |
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40 | #define LIBBSP_ARM_TMS570_RTI |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t COMPx; /*RTI Compare x Register*/ |
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46 | uint32_t UDCPx; /*RTI Update Compare x Register*/ |
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47 | } tms570_rti_compare_t; |
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48 | |
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49 | typedef struct{ |
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50 | uint32_t FRCx; /*RTI Free Running Counter x Register*/ |
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51 | uint32_t UCx; /*RTI Up Counter x Register*/ |
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52 | uint32_t CPUCx; /*RTI Compare Up Counter x Register*/ |
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53 | uint8_t reserved1 [4]; |
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54 | uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/ |
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55 | uint32_t CAUCx; /*RTI Capture Up Counter x Register*/ |
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56 | uint32_t rsvd[2]; /*Reserved*/ |
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57 | } tms570_rti_counter_t; |
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58 | |
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59 | typedef struct{ |
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60 | uint32_t GCTRL; /*RTI Global Control Register*/ |
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61 | uint32_t TBCTRL; /*RTI Timebase Control Register*/ |
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62 | uint32_t CAPCTRL; /*RTI Capture Control Register*/ |
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63 | uint32_t COMPCTRL; /*RTI Compare Control Register*/ |
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64 | tms570_rti_counter_t CNT[2];/*Counters*/ |
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65 | tms570_rti_compare_t CMP[4];/*Compares*/ |
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66 | uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/ |
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67 | uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/ |
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68 | uint8_t reserved2 [8]; |
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69 | uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/ |
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70 | uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/ |
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71 | uint32_t INTFLAG; /*RTI Interrupt Flag Register*/ |
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72 | uint8_t reserved3 [4]; |
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73 | uint32_t DWDCTRL; /*Digital Watchdog Control Register*/ |
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74 | uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/ |
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75 | uint32_t WDSTATUS; /*Watchdog Status Register*/ |
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76 | uint32_t WDKEY; /*RTI Watchdog Key Register*/ |
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77 | uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/ |
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78 | uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/ |
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79 | uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/ |
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80 | uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/ |
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81 | uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/ |
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82 | uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/ |
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83 | uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/ |
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84 | uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/ |
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85 | } tms570_rti_t; |
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86 | |
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87 | |
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88 | /*----------------------TMS570_RTI_COMPx----------------------*/ |
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89 | /* field: COMPx - Compare x. */ |
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90 | /* Whole 32 bits */ |
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91 | |
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92 | /*----------------------TMS570_RTI_UDCPx----------------------*/ |
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93 | /* field: UDCPx - Update compare x. */ |
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94 | /* Whole 32 bits */ |
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95 | |
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96 | /*----------------------TMS570_RTI_FRCx----------------------*/ |
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97 | /* field: FRC0 - FRC0 */ |
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98 | /* Whole 32 bits */ |
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99 | |
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100 | /*-----------------------TMS570_RTI_UCx-----------------------*/ |
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101 | /* field: UC0 - Up counter 0. */ |
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102 | /* Whole 32 bits */ |
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103 | |
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104 | /*----------------------TMS570_RTI_CPUCx----------------------*/ |
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105 | /* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */ |
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106 | /* Whole 32 bits */ |
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107 | |
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108 | /*---------------------TMS570_RTI_CAFRCx---------------------*/ |
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109 | /* field: CAFRC0 - Capture free running counter 0. */ |
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110 | /* Whole 32 bits */ |
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111 | |
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112 | /*----------------------TMS570_RTI_CAUCx----------------------*/ |
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113 | /* field: CAUC0 - Capture up counter 0. */ |
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114 | /* Whole 32 bits */ |
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115 | |
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116 | /*----------------------TMS570_RTI_rsvd----------------------*/ |
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117 | /* field: CAUC0 - Capture up counter 0. */ |
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118 | /* Whole 32 bits */ |
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119 | |
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120 | /*----------------------TMS570_RTI_GCTRL----------------------*/ |
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121 | /* field: NTUSEL - Select NTU signal. */ |
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122 | #define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19) |
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123 | #define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19) |
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124 | #define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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125 | |
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126 | /* field: COS - Continue on suspend. */ |
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127 | #define TMS570_RTI_GCTRL_COS BSP_BIT32(15) |
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128 | |
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129 | /* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */ |
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130 | #define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1) |
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131 | |
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132 | /* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */ |
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133 | #define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0) |
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134 | |
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135 | |
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136 | /*---------------------TMS570_RTI_TBCTRL---------------------*/ |
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137 | /* field: INC - Increment free running counter 0. */ |
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138 | #define TMS570_RTI_TBCTRL_INC BSP_BIT32(1) |
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139 | |
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140 | /* field: TBEXT - Timebase external. */ |
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141 | #define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0) |
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142 | |
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143 | |
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144 | /*---------------------TMS570_RTI_CAPCTRL---------------------*/ |
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145 | /* field: CAPCNTR1 - Capture counter 1. */ |
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146 | #define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1) |
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147 | |
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148 | /* field: CAPCNTR0 - Capture counter 0. */ |
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149 | #define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0) |
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150 | |
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151 | |
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152 | /*--------------------TMS570_RTI_COMPCTRL--------------------*/ |
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153 | /* field: COMPSEL3 - Compare select 3. */ |
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154 | #define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12) |
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155 | |
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156 | /* field: COMPSEL2 - Compare select 2. */ |
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157 | #define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8) |
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158 | |
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159 | /* field: COMPSEL1 - Compare select 1. */ |
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160 | #define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4) |
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161 | |
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162 | /* field: COMPSEL0 - Compare select 0. */ |
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163 | #define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0) |
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164 | |
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165 | |
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166 | /*---------------------TMS570_RTI_TBLCOMP---------------------*/ |
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167 | /* field: TBLCOMP - Timebase low compare value. */ |
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168 | /* Whole 32 bits */ |
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169 | |
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170 | /*---------------------TMS570_RTI_TBHCOMP---------------------*/ |
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171 | /* field: TBHCOMP - Timebase high compare value. */ |
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172 | /* Whole 32 bits */ |
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173 | |
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174 | /*--------------------TMS570_RTI_SETINTENA--------------------*/ |
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175 | /* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */ |
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176 | #define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18) |
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177 | |
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178 | /* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */ |
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179 | #define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17) |
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180 | |
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181 | /* field: SETTBINT - Set timebase interrupt. */ |
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182 | #define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16) |
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183 | |
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184 | /* field: SETDMA3 - Set compare DMA request 3. */ |
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185 | #define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11) |
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186 | |
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187 | /* field: SETDMA2 - Set compare DMA request 2. */ |
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188 | #define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10) |
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189 | |
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190 | /* field: SETDMA1 - Set compare DMA request 1. */ |
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191 | #define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9) |
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192 | |
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193 | /* field: SETDMA0 - Set compare DMA request 0. */ |
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194 | #define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8) |
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195 | |
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196 | /* field: SETINT3 - Set compare interrupt 3. */ |
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197 | #define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3) |
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198 | |
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199 | /* field: SETINT2 - Set compare interrupt 2. */ |
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200 | #define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2) |
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201 | |
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202 | /* field: SETINT1 - Set compare interrupt 1. */ |
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203 | #define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1) |
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204 | |
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205 | /* field: SETINT0 - Set compare interrupt 0. */ |
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206 | #define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0) |
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207 | |
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208 | |
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209 | /*-------------------TMS570_RTI_CLEARINTENA-------------------*/ |
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210 | /* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */ |
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211 | #define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18) |
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212 | |
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213 | /* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */ |
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214 | #define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17) |
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215 | |
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216 | /* field: CLEARTBINT - Clear timebase interrupt. */ |
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217 | #define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16) |
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218 | |
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219 | /* field: CLEARDMA3 - Clear compare DMA request 3. */ |
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220 | #define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11) |
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221 | |
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222 | /* field: CLEARDMA2 - Clear compare DMA request 2. */ |
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223 | #define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10) |
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224 | |
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225 | /* field: CLEARDMA1 - Clear compare DMA request 1. */ |
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226 | #define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9) |
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227 | |
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228 | /* field: CLEARDMA0 - Clear compare DMA request 0. */ |
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229 | #define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8) |
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230 | |
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231 | /* field: CLEARINT3 - Clear compare interrupt 3. */ |
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232 | #define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3) |
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233 | |
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234 | /* field: CLEARINT2 - Clear compare interrupt 2. */ |
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235 | #define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2) |
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236 | |
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237 | /* field: CLEARINT1 - Clear compare interrupt 1. */ |
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238 | #define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1) |
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239 | |
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240 | /* field: CLEARINT0 - Clear compare interrupt 0. */ |
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241 | #define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0) |
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242 | |
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243 | |
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244 | /*---------------------TMS570_RTI_INTFLAG---------------------*/ |
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245 | /* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */ |
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246 | #define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18) |
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247 | |
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248 | /* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */ |
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249 | #define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17) |
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250 | |
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251 | /* field: TBINT - Timebase interrupt flag. */ |
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252 | #define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16) |
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253 | |
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254 | /* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */ |
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255 | #define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3) |
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256 | |
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257 | /* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */ |
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258 | #define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2) |
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259 | |
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260 | /* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */ |
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261 | #define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1) |
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262 | |
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263 | /* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */ |
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264 | #define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0) |
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265 | |
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266 | |
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267 | /*---------------------TMS570_RTI_DWDCTRL---------------------*/ |
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268 | /* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */ |
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269 | /* Whole 32 bits */ |
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270 | |
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271 | /*---------------------TMS570_RTI_DWDPRLD---------------------*/ |
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272 | /* field: DWDPRLD - Digital Watchdog Preload Value. */ |
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273 | #define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15) |
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274 | #define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15) |
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275 | #define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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276 | |
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277 | |
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278 | /*--------------------TMS570_RTI_WDSTATUS--------------------*/ |
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279 | /* field: DWWD_ST - Windowed Watchdog Status */ |
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280 | #define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5) |
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281 | |
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282 | /* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */ |
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283 | #define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4) |
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284 | |
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285 | /* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */ |
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286 | #define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3) |
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287 | |
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288 | /* field: KEY_ST - Watchdog key status. */ |
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289 | #define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2) |
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290 | |
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291 | /* field: DWD_ST - DWD status. */ |
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292 | #define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1) |
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293 | |
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294 | |
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295 | /*----------------------TMS570_RTI_WDKEY----------------------*/ |
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296 | /* field: WDKEY - Watchdog key. These bits provide the key sequence location. */ |
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297 | #define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15) |
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298 | #define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15) |
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299 | #define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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300 | |
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301 | |
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302 | /*---------------------TMS570_RTI_DWDCNTR---------------------*/ |
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303 | /* field: DWDCNTR - DWD down counter. */ |
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304 | #define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24) |
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305 | #define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24) |
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306 | #define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24) |
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307 | |
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308 | |
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309 | /*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/ |
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310 | /* field: WWDRXN - The DWWD reaction */ |
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311 | #define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3) |
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312 | #define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3) |
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313 | #define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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314 | |
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315 | |
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316 | /*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/ |
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317 | /* field: WWDSIZE - The DWWD window size */ |
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318 | /* Whole 32 bits */ |
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319 | |
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320 | /*------------------TMS570_RTI_INTCLRENABLE------------------*/ |
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321 | /* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */ |
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322 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27) |
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323 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27) |
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324 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27) |
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325 | |
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326 | /* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */ |
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327 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19) |
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328 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19) |
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329 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19) |
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330 | |
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331 | /* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */ |
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332 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11) |
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333 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11) |
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334 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11) |
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335 | |
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336 | /* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */ |
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337 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3) |
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338 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3) |
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339 | #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3) |
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340 | |
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341 | |
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342 | /*--------------------TMS570_RTI_COMP0CLR--------------------*/ |
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343 | /* field: CMP0CLR - Compare 0 clear. */ |
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344 | /* Whole 32 bits */ |
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345 | |
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346 | /*--------------------TMS570_RTI_COMP1CLR--------------------*/ |
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347 | /* field: CMP0CLR - Compare 1 clear. */ |
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348 | /* Whole 32 bits */ |
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349 | |
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350 | /*--------------------TMS570_RTI_COMP2CLR--------------------*/ |
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351 | /* field: CMP2CLR - Compare 2 clear. */ |
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352 | /* Whole 32 bits */ |
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353 | |
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354 | /*--------------------TMS570_RTI_COMP3CLR--------------------*/ |
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355 | /* field: CMP3CLR - Compare 3 clear. */ |
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356 | /* Whole 32 bits */ |
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357 | |
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358 | |
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359 | #endif /* LIBBSP_ARM_TMS570_RTI */ |
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