source: rtems/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 23.9 KB
Line 
1/* The header file is generated by make_header.py from EMIF.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 *    list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 *    this list of conditions and the following disclaimer in the documentation
22 *    and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_EMIF
40#define LIBBSP_ARM_TMS570_EMIF
41
42#include <bsp/utility.h>
43
44typedef struct{
45  uint32_t MIDR;              /*Module ID Register*/
46  uint32_t AWCC;              /*Asynchronous Wait Cycle Configuration Register*/
47  uint32_t SDCR;              /*SDRAM Configuration Register*/
48  uint32_t SDRCR;             /*SDRAM Refresh Control Register*/
49  uint32_t CE2CFG;            /*Asynchronous 1 Configuration Register*/
50  uint32_t CE3CFG;            /*Asynchronous 2 Configuration Register*/
51  uint32_t CE4CFG;            /*Asynchronous 3 Configuration Register*/
52  uint32_t CE5CFG;            /*Asynchronous 4 Configuration Register*/
53  uint32_t SDTIMR;            /*SDRAM Timing Register*/
54  uint8_t reserved1 [24];
55  uint32_t SDSRETR;           /*SDRAM Self Refresh Exit Timing Register*/
56  uint32_t INTRAW;            /*EMIF Interrupt Raw Register*/
57  uint32_t INTMSK;            /*EMIF Interrupt Mask Register*/
58  uint32_t INTMSKSET;         /*EMIF Interrupt Mask Set Register*/
59  uint32_t INTMSKCLR;         /*EMIF Interrupt Mask Clear Register*/
60  uint8_t reserved2 [24];
61  uint32_t PMCR;              /*Page Mode Control Register*/
62} tms570_emif_t;
63
64
65/*----------------------TMS570_EMIF_MIDR----------------------*/
66/* field: REV - Module ID of EMIF. See the device-specific data manual. */
67/* Whole 32 bits */
68
69/*----------------------TMS570_EMIF_AWCC----------------------*/
70/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
71#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
72
73/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
74#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
75
76/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
77#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
78#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23)
79#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23)
80
81/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */
82#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21)
83#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21)
84#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21)
85
86/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */
87#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19)
88#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19)
89#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19)
90
91/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */
92#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17)
93#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17)
94#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
95
96/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */
97#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7)
98#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7)
99#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
100
101
102/*----------------------TMS570_EMIF_SDCR----------------------*/
103/* field: SR - Self-Refresh mode bit. */
104#define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
105
106/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
107#define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
108
109/* field: PDWR - Perform refreshes during power down. */
110#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
111
112/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
113#define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
114
115/* field: CL - CAS Latency. */
116#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
117#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11)
118#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
119
120/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
121#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
122
123/* field: IBANK - Internal SDRAM Bank size. */
124#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
125#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6)
126#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
127
128/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */
129#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2)
130#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2)
131#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
132
133
134/*---------------------TMS570_EMIF_SDRCR---------------------*/
135/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
136#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
137#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
138#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
139
140
141/*---------------------TMS570_EMIF_CE2CFG---------------------*/
142/* field: SS - Select Strobe bit. */
143#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
144
145/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
146#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
147
148/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
149#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
150#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
151#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
152
153/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
154#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
155#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
156#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
157
158/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
159#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
160#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
161#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
162
163/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
164#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
165#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
166#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
167
168/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
169#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
170#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
171#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
172
173/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
174#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
175#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
176#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
177
178/* field: TA - Minimum Turn-Around time. */
179#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3)
180#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
181#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
182
183/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
184#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1)
185#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
186#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
187
188
189/*---------------------TMS570_EMIF_CE3CFG---------------------*/
190/* field: SS - Select Strobe bit. */
191#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
192
193/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
194#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
195
196/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
197#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
198#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
199#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
200
201/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
202#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
203#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
204#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
205
206/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
207#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
208#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
209#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
210
211/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
212#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
213#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
214#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
215
216/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
217#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
218#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
219#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
220
221/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
222#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
223#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
224#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
225
226/* field: TA - Minimum Turn-Around time. */
227#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3)
228#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
229#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
230
231/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
232#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1)
233#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
234#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
235
236
237/*---------------------TMS570_EMIF_CE4CFG---------------------*/
238/* field: SS - Select Strobe bit. */
239#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
240
241/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
242#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
243
244/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
245#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
246#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
247#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
248
249/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
250#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
251#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
252#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
253
254/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
255#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
256#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
257#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
258
259/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
260#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
261#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
262#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
263
264/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
265#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
266#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
267#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
268
269/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
270#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
271#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
272#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
273
274/* field: TA - Minimum Turn-Around time. */
275#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3)
276#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
277#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
278
279/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
280#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1)
281#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
282#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
283
284
285/*---------------------TMS570_EMIF_CE5CFG---------------------*/
286/* field: SS - Select Strobe bit. */
287#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
288
289/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
290#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
291
292/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
293#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
294#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
295#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
296
297/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
298#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
299#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
300#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
301
302/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
303#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
304#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
305#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
306
307/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
308#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
309#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
310#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
311
312/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
313#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
314#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
315#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
316
317/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
318#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
319#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
320#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
321
322/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */
323#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3)
324#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
325#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
326
327/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
328#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1)
329#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
330#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
331
332
333/*---------------------TMS570_EMIF_SDTIMR---------------------*/
334/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
335#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
336#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
337#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31)
338
339/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */
340#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26)
341#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26)
342#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
343
344/* field: T_RCD - Specifies the Trcd value of the SDRAM. */
345#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22)
346#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22)
347#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
348
349/* field: T_WR - Specifies the Twr value of the SDRAM. */
350#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18)
351#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18)
352#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
353
354/* field: T_RAS - Specifies the Tras value of the SDRAM. */
355#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15)
356#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15)
357#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
358
359/* field: T_RC - Specifies the Trc value of the SDRAM. */
360#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11)
361#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11)
362#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
363
364/* field: T_RRD - Specifies the Trrd value of the SDRAM. */
365#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6)
366#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6)
367#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
368
369
370/*--------------------TMS570_EMIF_SDSRETR--------------------*/
371/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
372#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
373#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
374#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
375
376
377/*---------------------TMS570_EMIF_INTRAW---------------------*/
378/* field: WR - Wait Rise. */
379#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
380
381/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
382#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
383
384/* field: AT - Asynchronous Timeout. */
385#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
386
387
388/*---------------------TMS570_EMIF_INTMSK---------------------*/
389/* field: WR_MASKED - Wait Rise Masked. */
390#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
391
392/* field: LT_MASKED - Masked Line Trap. */
393#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
394
395/* field: AT_MASKED - Asynchronous Timeout Masked. */
396#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
397
398
399/*-------------------TMS570_EMIF_INTMSKSET-------------------*/
400/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
401#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
402
403/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
404#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
405
406/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
407#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
408
409
410/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
411/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
412#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
413
414/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
415#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
416
417/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
418#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
419
420
421/*----------------------TMS570_EMIF_PMCR----------------------*/
422/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
423#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
424#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
425#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
426
427/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
428#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
429
430/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
431#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
432
433/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
434#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
435#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23)
436#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
437
438/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
439#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
440
441/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
442#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
443
444/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
445#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
446#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15)
447#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
448
449/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
450#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
451
452/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
453#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
454
455/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
456#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
457#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7)
458#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
459
460/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
461#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
462
463/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
464#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
465
466
467
468#endif /* LIBBSP_ARM_TMS570_EMIF */
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