1 | /* The header file is generated by make_header.py from CRC.json */ |
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2 | /* Current script's version can be found at: */ |
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3 | /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> |
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7 | * |
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8 | * Czech Technical University in Prague |
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9 | * Zikova 1903/4 |
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10 | * 166 36 Praha 6 |
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11 | * Czech Republic |
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12 | * |
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13 | * All rights reserved. |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions are met: |
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17 | * |
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18 | * 1. Redistributions of source code must retain the above copyright notice, this |
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19 | * list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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21 | * this list of conditions and the following disclaimer in the documentation |
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22 | * and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR |
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28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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31 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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34 | * |
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35 | * The views and conclusions contained in the software and documentation are those |
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36 | * of the authors and should not be interpreted as representing official policies, |
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37 | * either expressed or implied, of the FreeBSD Project. |
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38 | */ |
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39 | #ifndef LIBBSP_ARM_TMS570_CRC |
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40 | #define LIBBSP_ARM_TMS570_CRC |
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41 | |
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42 | #include <bsp/utility.h> |
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43 | |
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44 | typedef struct{ |
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45 | uint32_t CTRL0; /*CRC Global Control Register*/ |
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46 | uint8_t reserved1 [4]; |
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47 | uint32_t CTRL1; /*CRC Global Control Register 1*/ |
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48 | uint8_t reserved2 [4]; |
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49 | uint32_t CTRL2; /*CRC Global Control Register 2*/ |
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50 | uint8_t reserved3 [4]; |
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51 | uint32_t INTS; /*CRC Interrupt Enable Set Register*/ |
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52 | uint8_t reserved4 [4]; |
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53 | uint32_t INTR; /*CRC Interrupt Enable Reset Register*/ |
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54 | uint8_t reserved5 [4]; |
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55 | uint32_t STATUS; /*CRC Interrupt Status Register*/ |
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56 | uint8_t reserved6 [4]; |
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57 | uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/ |
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58 | uint8_t reserved7 [4]; |
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59 | uint32_t BUSY; /*CRC Busy Register*/ |
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60 | uint8_t reserved8 [4]; |
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61 | uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/ |
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62 | uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/ |
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63 | uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/ |
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64 | uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/ |
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65 | uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/ |
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66 | uint8_t reserved9 [12]; |
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67 | uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/ |
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68 | uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/ |
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69 | uint32_t REGL1; /*Channel 1 CRC Value Low Register*/ |
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70 | uint32_t REGH1; /*Channel 1 CRC Value High Register*/ |
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71 | uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/ |
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72 | uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/ |
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73 | uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/ |
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74 | uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/ |
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75 | uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/ |
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76 | uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/ |
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77 | uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/ |
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78 | uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/ |
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79 | uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/ |
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80 | uint8_t reserved10 [12]; |
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81 | uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/ |
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82 | uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/ |
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83 | uint32_t REGL2; /*Channel 2 CRC Value Low Register*/ |
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84 | uint32_t REGH2; /*Channel 2 CRC Value High Register*/ |
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85 | uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/ |
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86 | uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/ |
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87 | uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/ |
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88 | uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/ |
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89 | uint8_t reserved11 [128]; |
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90 | uint32_t BUS_SEL; /*Data Bus Selection Register*/ |
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91 | } tms570_crc_t; |
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92 | |
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93 | |
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94 | /*----------------------TMS570_CRC_CTRL0----------------------*/ |
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95 | /* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ |
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96 | #define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8) |
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97 | |
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98 | /* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ |
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99 | #define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0) |
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100 | |
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101 | |
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102 | /*----------------------TMS570_CRC_CTRL1----------------------*/ |
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103 | /* field: PWDN - Power Down. */ |
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104 | #define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0) |
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105 | |
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106 | |
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107 | /*----------------------TMS570_CRC_CTRL2----------------------*/ |
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108 | /* field: CH2_MODE - Channel 2 Mode Selection */ |
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109 | #define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9) |
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110 | #define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) |
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111 | #define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) |
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112 | |
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113 | /* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */ |
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114 | #define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4) |
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115 | |
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116 | /* field: CH1_MODE - Channel 1 Mode Selection */ |
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117 | #define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1) |
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118 | #define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1) |
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119 | #define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) |
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120 | |
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121 | |
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122 | /*----------------------TMS570_CRC_INTS----------------------*/ |
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123 | /* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */ |
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124 | #define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12) |
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125 | |
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126 | /* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */ |
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127 | #define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11) |
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128 | |
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129 | /* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */ |
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130 | #define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10) |
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131 | |
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132 | /* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */ |
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133 | #define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9) |
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134 | |
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135 | /* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */ |
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136 | #define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8) |
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137 | |
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138 | /* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */ |
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139 | #define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4) |
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140 | |
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141 | /* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */ |
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142 | #define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3) |
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143 | |
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144 | /* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */ |
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145 | #define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2) |
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146 | |
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147 | /* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */ |
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148 | #define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1) |
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149 | |
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150 | /* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */ |
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151 | #define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0) |
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152 | |
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153 | |
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154 | /*----------------------TMS570_CRC_INTR----------------------*/ |
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155 | /* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */ |
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156 | #define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12) |
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157 | |
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158 | /* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */ |
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159 | #define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11) |
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160 | |
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161 | /* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */ |
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162 | #define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10) |
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163 | |
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164 | /* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */ |
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165 | #define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9) |
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166 | |
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167 | /* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */ |
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168 | #define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8) |
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169 | |
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170 | /* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */ |
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171 | #define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4) |
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172 | |
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173 | /* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */ |
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174 | #define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3) |
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175 | |
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176 | /* field: CH1_OVERENR - CH1_OVERENR */ |
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177 | #define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2) |
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178 | |
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179 | /* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */ |
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180 | #define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1) |
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181 | |
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182 | /* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */ |
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183 | #define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0) |
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184 | |
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185 | |
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186 | /*---------------------TMS570_CRC_STATUS---------------------*/ |
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187 | /* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */ |
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188 | #define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12) |
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189 | |
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190 | /* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */ |
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191 | #define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11) |
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192 | |
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193 | /* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */ |
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194 | #define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10) |
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195 | |
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196 | /* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */ |
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197 | #define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9) |
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198 | |
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199 | /* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */ |
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200 | #define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8) |
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201 | |
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202 | /* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */ |
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203 | #define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4) |
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204 | |
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205 | /* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */ |
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206 | #define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3) |
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207 | |
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208 | /* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */ |
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209 | #define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2) |
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210 | |
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211 | /* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */ |
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212 | #define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1) |
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213 | |
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214 | /* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */ |
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215 | #define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0) |
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216 | |
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217 | |
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218 | /*------------------TMS570_CRC_INT_OFFS_REG------------------*/ |
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219 | /* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */ |
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220 | #define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7) |
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221 | #define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7) |
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222 | #define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) |
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223 | |
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224 | |
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225 | /*----------------------TMS570_CRC_BUSY----------------------*/ |
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226 | /* field: CH2_BUSY - CH2_BUSY. */ |
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227 | #define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8) |
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228 | |
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229 | /* field: CH1_BUSY - CH1_BUSY. */ |
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230 | #define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0) |
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231 | |
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232 | |
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233 | /*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/ |
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234 | /* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */ |
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235 | #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19) |
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236 | #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) |
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237 | #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) |
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238 | |
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239 | |
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240 | /*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/ |
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241 | /* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */ |
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242 | #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15) |
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243 | #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15) |
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244 | #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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245 | |
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246 | |
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247 | /*-------------------TMS570_CRC_CURSEC_REG1-------------------*/ |
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248 | /* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */ |
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249 | #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15) |
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250 | #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15) |
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251 | #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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252 | |
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253 | |
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254 | /*--------------------TMS570_CRC_WDTOPLD1--------------------*/ |
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255 | /* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */ |
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256 | #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23) |
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257 | #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) |
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258 | #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) |
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259 | |
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260 | |
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261 | /*--------------------TMS570_CRC_BCTOPLD1--------------------*/ |
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262 | /* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */ |
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263 | #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23) |
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264 | #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) |
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265 | #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) |
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266 | |
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267 | |
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268 | /*------------------TMS570_CRC_PSA_SIGREGL1------------------*/ |
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269 | /* field: PSASIG1 - Channel 1 PSA Signature Low Register. */ |
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270 | /* Whole 32 bits */ |
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271 | |
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272 | /*------------------TMS570_CRC_PSA_SIGREGH1------------------*/ |
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273 | /* field: PSASIG1 - register. */ |
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274 | /* Whole 32 bits */ |
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275 | |
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276 | /*----------------------TMS570_CRC_REGL1----------------------*/ |
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277 | /* field: CRC1 - Channel 1 CRC Value Low Register. */ |
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278 | /* Whole 32 bits */ |
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279 | |
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280 | /*----------------------TMS570_CRC_REGH1----------------------*/ |
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281 | /* field: CRC1 - Channel 1 CRC Value Low Register. */ |
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282 | /* Whole 32 bits */ |
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283 | |
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284 | /*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/ |
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285 | /* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */ |
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286 | /* Whole 32 bits */ |
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287 | |
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288 | /*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/ |
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289 | /* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */ |
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290 | /* Whole 32 bits */ |
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291 | |
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292 | /*------------------TMS570_CRC_RAW_DATAREGL1------------------*/ |
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293 | /* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */ |
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294 | /* Whole 32 bits */ |
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295 | |
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296 | /*------------------TMS570_CRC_RAW_DATAREGH1------------------*/ |
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297 | /* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */ |
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298 | /* Whole 32 bits */ |
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299 | |
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300 | /*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/ |
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301 | /* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */ |
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302 | #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19) |
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303 | #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19) |
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304 | #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) |
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305 | |
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306 | |
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307 | /*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/ |
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308 | /* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */ |
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309 | #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15) |
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310 | #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15) |
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311 | #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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312 | |
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313 | |
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314 | /*-------------------TMS570_CRC_CURSEC_REG2-------------------*/ |
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315 | /* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */ |
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316 | #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15) |
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317 | #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15) |
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318 | #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) |
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319 | |
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320 | |
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321 | /*--------------------TMS570_CRC_WDTOPLD2--------------------*/ |
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322 | /* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */ |
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323 | #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23) |
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324 | #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) |
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325 | #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) |
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326 | |
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327 | |
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328 | /*--------------------TMS570_CRC_BCTOPLD2--------------------*/ |
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329 | /* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */ |
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330 | #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23) |
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331 | #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) |
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332 | #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) |
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333 | |
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334 | |
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335 | /*------------------TMS570_CRC_PSA_SIGREGL2------------------*/ |
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336 | /* field: PSASIG2 - Channel 2 PSA Signature Low Register. */ |
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337 | /* Whole 32 bits */ |
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338 | |
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339 | /*------------------TMS570_CRC_PSA_SIGREGH2------------------*/ |
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340 | /* field: PSASIG2 - Channel 2 PSA Signature High Register. */ |
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341 | /* Whole 32 bits */ |
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342 | |
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343 | /*----------------------TMS570_CRC_REGL2----------------------*/ |
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344 | /* field: CRC2 - stored at CRC2[31:0] register. */ |
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345 | /* Whole 32 bits */ |
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346 | |
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347 | /*----------------------TMS570_CRC_REGH2----------------------*/ |
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348 | /* field: CRC2 - Channel 2 CRC Value High Register. */ |
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349 | /* Whole 32 bits */ |
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350 | |
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351 | /*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/ |
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352 | /* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */ |
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353 | /* Whole 32 bits */ |
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354 | |
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355 | /*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/ |
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356 | /* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */ |
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357 | /* Whole 32 bits */ |
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358 | |
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359 | /*------------------TMS570_CRC_RAW_DATAREGL2------------------*/ |
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360 | /* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */ |
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361 | /* Whole 32 bits */ |
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362 | |
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363 | /*------------------TMS570_CRC_RAW_DATAREGH2------------------*/ |
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364 | /* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */ |
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365 | /* Whole 32 bits */ |
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366 | |
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367 | /*---------------------TMS570_CRC_BUS_SEL---------------------*/ |
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368 | /* field: MEn - Enable/disables the tracing of Peripheral Bus Master */ |
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369 | #define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2) |
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370 | |
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371 | /* field: DTCMEn - Enable/disables the tracing of data TCM */ |
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372 | #define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1) |
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373 | |
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374 | /* field: ITCMEn - Enable/disables the tracing of instruction TCM */ |
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375 | #define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0) |
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376 | |
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377 | |
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378 | |
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379 | #endif /* LIBBSP_ARM_TMS570_CRC */ |
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