source: rtems/bsps/arm/stm32h7/start/stm32h7-hal.c @ 99494370

Last change on this file since 99494370 was 99494370, checked in by Sebastian Huber <sebastian.huber@…>, on 03/04/20 at 11:34:34

bsp/stm32h7: New BSP

Update #3910.
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifdef HAVE_CONFIG_H
29#include "config.h"
30#endif
31
32#include <stm32h7/hal.h>
33
34#include <rtems.h>
35
36stm32h7_module_index stm32h7_get_module_index(const void *regs)
37{
38  switch ((uintptr_t) regs) {
39    case GPIOA_BASE:
40      return STM32H7_MODULE_GPIOA;
41    case GPIOB_BASE:
42      return STM32H7_MODULE_GPIOB;
43    case GPIOC_BASE:
44      return STM32H7_MODULE_GPIOC;
45    case GPIOD_BASE:
46      return STM32H7_MODULE_GPIOD;
47    case GPIOE_BASE:
48      return STM32H7_MODULE_GPIOE;
49    case GPIOF_BASE:
50      return STM32H7_MODULE_GPIOF;
51    case GPIOG_BASE:
52      return STM32H7_MODULE_GPIOG;
53    case GPIOH_BASE:
54      return STM32H7_MODULE_GPIOH;
55    case GPIOI_BASE:
56      return STM32H7_MODULE_GPIOI;
57    case GPIOJ_BASE:
58      return STM32H7_MODULE_GPIOJ;
59    case GPIOK_BASE:
60      return STM32H7_MODULE_GPIOK;
61    case USART1_BASE:
62      return STM32H7_MODULE_USART1;
63    case USART2_BASE:
64      return STM32H7_MODULE_USART2;
65    case USART3_BASE:
66      return STM32H7_MODULE_USART3;
67    case UART4_BASE:
68      return STM32H7_MODULE_UART4;
69    case UART5_BASE:
70      return STM32H7_MODULE_UART5;
71    case USART6_BASE:
72      return STM32H7_MODULE_USART6;
73    case UART7_BASE:
74      return STM32H7_MODULE_UART7;
75    case UART8_BASE:
76      return STM32H7_MODULE_UART8;
77#ifdef UART9_BASE
78    case UART9_BASE:
79      return STM32H7_MODULE_UART9;
80#endif
81#ifdef USART10_BASE
82    case USART10_BASE:
83      return STM32H7_MODULE_USART10;
84#endif
85    case RNG_BASE:
86      return STM32H7_MODULE_RNG;
87  }
88
89  return STM32H7_MODULE_INVALID;
90}
91
92typedef struct {
93  __IO uint32_t *enr;
94  uint32_t enable_bit;
95} stm32h7_clk_info;
96
97static const stm32h7_clk_info stm32h7_clk[] = {
98  [STM32H7_MODULE_INVALID] = { NULL, 0 },
99  [STM32H7_MODULE_GPIOA] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN },
100  [STM32H7_MODULE_GPIOB] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN },
101  [STM32H7_MODULE_GPIOC] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN },
102  [STM32H7_MODULE_GPIOD] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN },
103  [STM32H7_MODULE_GPIOE] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN },
104  [STM32H7_MODULE_GPIOF] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN },
105  [STM32H7_MODULE_GPIOG] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN },
106  [STM32H7_MODULE_GPIOH] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN },
107  [STM32H7_MODULE_GPIOI] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN },
108  [STM32H7_MODULE_GPIOJ] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN },
109  [STM32H7_MODULE_GPIOK] = { &RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN },
110  [STM32H7_MODULE_USART1] = { &RCC->APB2ENR, RCC_APB2ENR_USART1EN },
111  [STM32H7_MODULE_USART2] = { &RCC->APB1LENR, RCC_APB1LENR_USART2EN },
112  [STM32H7_MODULE_USART3] = { &RCC->APB1LENR, RCC_APB1LENR_USART3EN },
113  [STM32H7_MODULE_UART4] = { &RCC->APB1LENR, RCC_APB1LENR_UART4EN },
114  [STM32H7_MODULE_UART5] = { &RCC->APB1LENR, RCC_APB1LENR_UART5EN },
115  [STM32H7_MODULE_USART6] = { &RCC->APB2ENR, RCC_APB2ENR_USART6EN },
116  [STM32H7_MODULE_UART7] = { &RCC->APB1LENR, RCC_APB1LENR_UART7EN },
117  [STM32H7_MODULE_UART8] = { &RCC->APB1LENR, RCC_APB1LENR_UART8EN },
118#ifdef UART9_BASE
119  [STM32H7_MODULE_UART9] = { &RCC->APB2ENR, RCC_APB2ENR_UART9EN },
120#else
121  [STM32H7_MODULE_UART9] = { NULL, 0 },
122#endif
123#ifdef USART10_BASE
124  [STM32H7_MODULE_USART10] = { &RCC->APB2ENR, RCC_APB2ENR_USART10EN },
125#else
126  [STM32H7_MODULE_USART10] = { NULL, 0 },
127#endif
128  [STM32H7_MODULE_RNG] = { &RCC->AHB2ENR, RCC_AHB2ENR_RNGEN },
129  [STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN },
130  [STM32H7_MODULE_ETH1TX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN },
131  [STM32H7_MODULE_ETH1RX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN },
132  [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN },
133  [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN },
134  [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN },
135  [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN }
136};
137
138void stm32h7_clk_enable(stm32h7_module_index index)
139{
140  __IO uint32_t *enr;
141  uint32_t enable_bit;
142  rtems_interrupt_level level;
143
144  enr = stm32h7_clk[index].enr;
145  enable_bit = stm32h7_clk[index].enable_bit;
146
147  rtems_interrupt_disable(level);
148  SET_BIT(*enr, enable_bit);
149  /* Delay after an RCC peripheral clock enabling */
150  *enr;
151  rtems_interrupt_enable(level);
152}
153
154void stm32h7_clk_disable(stm32h7_module_index index)
155{
156  __IO uint32_t *enr;
157  uint32_t enable_bit;
158  rtems_interrupt_level level;
159
160  enr = stm32h7_clk[index].enr;
161  enable_bit = stm32h7_clk[index].enable_bit;
162
163  rtems_interrupt_disable(level);
164  CLEAR_BIT(*enr, enable_bit);
165  rtems_interrupt_enable(level);
166}
167
168static const stm32h7_clk_info stm32h7_clk_low_power[] = {
169  [STM32H7_MODULE_INVALID] = { NULL, 0 },
170  [STM32H7_MODULE_GPIOA] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN },
171  [STM32H7_MODULE_GPIOB] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN },
172  [STM32H7_MODULE_GPIOC] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN },
173  [STM32H7_MODULE_GPIOD] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN },
174  [STM32H7_MODULE_GPIOE] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN },
175  [STM32H7_MODULE_GPIOF] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN },
176  [STM32H7_MODULE_GPIOG] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN },
177  [STM32H7_MODULE_GPIOH] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN },
178  [STM32H7_MODULE_GPIOI] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOILPEN },
179  [STM32H7_MODULE_GPIOJ] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOJLPEN },
180  [STM32H7_MODULE_GPIOK] = { &RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOKLPEN },
181  [STM32H7_MODULE_USART1] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN },
182  [STM32H7_MODULE_USART2] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN },
183  [STM32H7_MODULE_USART3] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN },
184  [STM32H7_MODULE_UART4] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN },
185  [STM32H7_MODULE_UART5] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN },
186  [STM32H7_MODULE_USART6] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART6LPEN },
187  [STM32H7_MODULE_UART7] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN },
188  [STM32H7_MODULE_UART8] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN },
189#ifdef UART9_BASE
190  [STM32H7_MODULE_UART9] = { &RCC->APB2LPENR, RCC_APB2LPENR_UART9LPEN },
191#else
192  [STM32H7_MODULE_UART9] = { NULL, 0 },
193#endif
194#ifdef USART10_BASE
195  [STM32H7_MODULE_USART10] = { &RCC->APB2LPENR, RCC_APB2LPENR_USART10LPEN },
196#else
197  [STM32H7_MODULE_USART10] = { NULL, 0 },
198#endif
199  [STM32H7_MODULE_RNG] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN },
200  [STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN },
201  [STM32H7_MODULE_ETH1TX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN },
202  [STM32H7_MODULE_ETH1RX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN },
203  [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSLPEN },
204  [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSULPILPEN },
205  [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSLPEN },
206  [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN }
207};
208
209void stm32h7_clk_low_power_enable(stm32h7_module_index index)
210{
211  __IO uint32_t *enr;
212  uint32_t enable_bit;
213  rtems_interrupt_level level;
214
215  enr = stm32h7_clk_low_power[index].enr;
216  enable_bit = stm32h7_clk_low_power[index].enable_bit;
217
218  rtems_interrupt_disable(level);
219  SET_BIT(*enr, enable_bit);
220  /* Delay after an RCC peripheral clock enabling */
221  *enr;
222  rtems_interrupt_enable(level);
223}
224
225void stm32h7_clk_low_power_disable(stm32h7_module_index index)
226{
227  __IO uint32_t *enr;
228  uint32_t enable_bit;
229  rtems_interrupt_level level;
230
231  enr = stm32h7_clk_low_power[index].enr;
232  enable_bit = stm32h7_clk_low_power[index].enable_bit;
233
234  rtems_interrupt_disable(level);
235  CLEAR_BIT(*enr, enable_bit);
236  rtems_interrupt_enable(level);
237}
238
239void stm32h7_gpio_init(const stm32h7_gpio_config *config)
240{
241  stm32h7_module_index index;
242
243  index = stm32h7_get_module_index(config->regs);
244  stm32h7_clk_enable(index);
245  HAL_GPIO_Init(config->regs, &config->config);
246}
247
248void stm32h7_uart_polled_write(rtems_termios_device_context *base, char c)
249{
250  stm32h7_uart_context *ctx;
251  USART_TypeDef *regs;
252
253  ctx = stm32h7_uart_get_context(base);
254  regs = ctx->uart.Instance;
255
256  while ((regs->ISR & USART_ISR_TXE_TXFNF) == 0) {
257    /* Wait */
258  }
259
260  regs->TDR = (uint8_t) c;
261}
262
263int stm32h7_uart_polled_read(rtems_termios_device_context *base)
264{
265  stm32h7_uart_context *ctx;
266  USART_TypeDef *regs;
267
268  ctx = stm32h7_uart_get_context(base);
269  regs = ctx->uart.Instance;
270
271  if ((regs->ISR & USART_ISR_RXNE_RXFNE) == 0) {
272    return -1;
273  }
274
275  return (uint8_t) regs->RDR;
276}
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