source: rtems/bsps/arm/stm32h7/start/stm32h7-hal-eth.c @ b24e8142

Last change on this file since b24e8142 was b24e8142, checked in by Robin Mueller <robin.mueller.m@…>, on 07/16/21 at 12:32:03

STM32H7 ethernet pin corrections

These patches were submitted a few months ago, but it was found out
that the default-by-family: [] were missing in the GPIO .yml lines.
This was fixed in this patch.

This patch accounts for different pins for the ETH peripheral
on STM32H7 devices. For example, the Nucleo H743ZI has slightly
different pins than other STM32H7 boards.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifdef HAVE_CONFIG_H
29#include "config.h"
30#endif
31
32#include <stm32h7/hal.h>
33
34#include <bspopts.h>
35
36static const stm32h7_gpio_config gpiog = {
37  .regs = GPIOG,
38  .config = {
39    .Pin = STM32H7_ETH_GPIOG_PINS,
40    .Mode = GPIO_MODE_AF_PP,
41    .Pull = GPIO_NOPULL,
42    .Speed = GPIO_SPEED_FREQ_LOW,
43    .Alternate = GPIO_AF11_ETH
44  }
45};
46
47static const stm32h7_gpio_config gpioc = {
48  .regs = GPIOC,
49  .config = {
50    .Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5,
51    .Mode = GPIO_MODE_AF_PP,
52    .Pull = GPIO_NOPULL,
53    .Speed = GPIO_SPEED_FREQ_LOW,
54    .Alternate = GPIO_AF11_ETH
55  }
56};
57
58static const stm32h7_gpio_config gpioa = {
59  .regs = GPIOA,
60  .config = {
61    .Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7,
62    .Mode = GPIO_MODE_AF_PP,
63    .Pull = GPIO_NOPULL,
64    .Speed = GPIO_SPEED_FREQ_LOW,
65    .Alternate = GPIO_AF11_ETH
66  }
67};
68
69#ifdef STM32H7_ETH_GPIOB_PINS
70
71static const stm32h7_gpio_config gpiob = {
72  .regs = GPIOB,
73  .config = {
74    .Pin = STM32H7_ETH_GPIOB_PINS,
75    .Mode = GPIO_MODE_AF_PP,
76    .Pull = GPIO_NOPULL,
77    .Speed = GPIO_SPEED_FREQ_LOW,
78    .Alternate = GPIO_AF11_ETH
79  }
80};
81
82#endif
83
84void
85HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
86{
87  stm32h7_clk_enable(STM32H7_MODULE_ETH1MAC);
88  stm32h7_clk_enable(STM32H7_MODULE_ETH1TX);
89  stm32h7_clk_enable(STM32H7_MODULE_ETH1RX);
90  stm32h7_gpio_init(&gpiog);
91  stm32h7_gpio_init(&gpioc);
92  stm32h7_gpio_init(&gpioa);
93#ifdef STM32H7_ETH_GPIOB_PINS
94  stm32h7_gpio_init(&gpiob);
95#endif
96}
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