source: rtems/bsps/arm/stm32h7/start/ext-mem-ctl.c @ 99494370

Last change on this file since 99494370 was 99494370, checked in by Sebastian Huber <sebastian.huber@…>, on 03/04/20 at 11:34:34

bsp/stm32h7: New BSP

Update #3910.
  • Property mode set to 100644
File size: 17.1 KB
Line 
1/**
2  ******************************************************************************
3  * @file    system_stm32h7xx.c
4  * @author  MCD Application Team
5  * @brief   CMSIS Cortex-M Device Peripheral Access Layer System Source File.
6  *
7  *   This file provides two functions and one global variable to be called from
8  *   user application:
9  *      - SystemInit(): This function is called at startup just after reset and
10  *                      before branch to main program. This call is made inside
11  *                      the "startup_stm32h7xx.s" file.
12  *
13  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14  *                                  by the user application to setup the SysTick
15  *                                  timer or configure other parameters.
16  *                                     
17  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18  *                                 be called whenever the core clock is changed
19  *                                 during program execution.
20  *
21  *
22  ******************************************************************************
23  * @attention
24  *
25  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26  * All rights reserved.</center></h2>
27  *
28  * This software component is licensed by ST under BSD 3-Clause license,
29  * the "License"; You may not use this file except in compliance with the
30  * License. You may obtain a copy of the License at:
31  *                        opensource.org/licenses/BSD-3-Clause
32  *
33  ******************************************************************************
34  */
35
36#include <stm32h7xx_hal.h>
37
38#define DATA_IN_ExtSRAM
39#define DATA_IN_ExtSDRAM
40
41void  SystemInit_ExtMemCtl(void)
42{
43
44  #define  FMC_BMAP_Value    0x02000000    /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
45
46  __IO uint32_t  tmp = 0;
47
48
49  /********** SDRAM + SRAM ***********************************************************************/
50
51  #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
52
53  register uint32_t       tmpreg = 0, timeout = 0xFFFF;
54  register __IO uint32_t  index;
55 
56  /*-- I/O Ports Configuration ------------------------------------------------------*/
57
58  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
59  RCC->AHB4ENR |= 0x000001F8;
60 
61  /* Delay after an RCC peripheral clock enabling */
62  tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
63 
64  /* Connect PDx pins to FMC Alternate function */     
65  GPIOD->AFR[0]  = 0x00CC00CC;
66  GPIOD->AFR[1]  = 0xCCCCCCCC;
67  /* Configure PDx pins in Alternate function mode */ 
68  GPIOD->MODER   = 0xAAAAFAFA;
69  /* Configure PDx pins speed to VERY_HIGH */ 
70  GPIOD->OSPEEDR = 0xFFFFFF0F;
71  /* Configure PDx pins Output type to push-pull */ 
72  GPIOD->OTYPER  = 0x00000000;
73  /* Configure PDx pins in Pull-up */
74  GPIOD->PUPDR   = 0x55550505;
75
76  /* Connect PEx pins to FMC Alternate function */
77  GPIOE->AFR[0]  = 0xC00CC0CC;
78  GPIOE->AFR[1]  = 0xCCCCCCCC;
79  /* Configure PEx pins in Alternate function mode */
80  GPIOE->MODER   = 0xAAAABEBA;
81  /* Configure PEx pins speed to VERY_HIGH */
82  GPIOE->OSPEEDR = 0xFFFFFFFF;
83  /* Configure PEx pins Output type to push-pull */ 
84  GPIOE->OTYPER  = 0x00000000;
85  /* Configure PEx pins in Pull-up */
86  GPIOE->PUPDR   = 0x55554145;
87
88  /* Connect PFx pins to FMC Alternate function */
89  GPIOF->AFR[0]  = 0x00CCCCCC;
90  GPIOF->AFR[1]  = 0xCCCCC000;
91  /* Configure PFx pins in Alternate function mode */   
92  GPIOF->MODER   = 0xAABFFAAA;
93  /* Configure PFx pins speed to VERY_HIGH */
94  GPIOF->OSPEEDR = 0xFFC00FFF;
95  /* Configure PFx pins Output type to push-pull */ 
96  GPIOF->OTYPER  = 0x00000000;
97  /* Configure PFx pins in Pull-up */
98  GPIOF->PUPDR   = 0x55400555;
99
100  /* Connect PGx pins to FMC Alternate function */
101  GPIOG->AFR[0]  = 0x00CCCCCC;
102  GPIOG->AFR[1]  = 0xC0000C0C;
103  /* Configure PGx pins in Alternate function mode */
104  GPIOG->MODER   = 0xBFEEFAAA;
105  /* Configure PGx pins speed to VERY_HIGH */
106  GPIOG->OSPEEDR = 0xC0330FFF;
107  /* Configure PGx pins Output type to push-pull */ 
108  GPIOG->OTYPER  = 0x00000000;
109  /* Configure PGx pins in Pull-up */
110  GPIOG->PUPDR   = 0x40110555;
111 
112  /* Connect PHx pins to FMC Alternate function */
113  GPIOH->AFR[0]  = 0xCCC00000;
114  GPIOH->AFR[1]  = 0xCCCCCCCC;
115  /* Configure PHx pins in Alternate function mode */
116  GPIOH->MODER   = 0xAAAAABFF;
117  /* Configure PHx pins speed to VERY_HIGH */
118  GPIOH->OSPEEDR = 0xFFFFFC00;
119  /* Configure PHx pins Output type to push-pull */ 
120  GPIOH->OTYPER  = 0x00000000;
121  /* Configure PHx pins in Pull-up */
122  GPIOH->PUPDR   = 0x55555400;
123 
124  /* Connect PIx pins to FMC Alternate function */
125  GPIOI->AFR[0]  = 0xCCCCCCCC;
126  GPIOI->AFR[1]  = 0x00000CC0;
127  /* Configure PIx pins in Alternate function mode */
128  GPIOI->MODER   = 0xFFEBAAAA;
129  /* Configure PIx pins speed to VERY_HIGH */
130  GPIOI->OSPEEDR = 0x003CFFFF;
131  /* Configure PIx pins Output type to push-pull */ 
132  GPIOI->OTYPER  = 0x00000000;
133  /* Configure PIx pins in Pull-up */
134  GPIOI->PUPDR   = 0x00145555;
135
136  /*-- FMC Configuration ------------------------------------------------------*/
137
138  /* Enable the FMC/FSMC interface clock */
139  (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
140 
141  /* Configure and enable Bank1_SRAM2 */
142  FMC_Bank1_R->BTCR[4]  = 0x00001091;
143  FMC_Bank1_R->BTCR[5]  = 0x00110212;
144  FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
145 
146  /* SDRAM Timing and access interface configuration */
147
148  /*SDBank               = FMC_SDRAM_BANK2
149
150    ColumnBitsNumber     = FMC_SDRAM_COLUMN_BITS_NUM_9           CC
151    RowBitsNumber        = FMC_SDRAM_ROW_BITS_NUM_12             RR
152    MemoryDataWidth      = FMC_SDRAM_MEM_BUS_WIDTH_32            MM
153    InternalBankNumber   = FMC_SDRAM_INTERN_BANKS_NUM_4          N
154    CASLatency           = FMC_SDRAM_CAS_LATENCY_2               LL   // 2 oder 3, s.u.
155    WriteProtection      = FMC_SDRAM_WRITE_PROTECTION_DISABLE    W
156    SDClockPeriod        = FMC_SDRAM_CLOCK_PERIOD_2              KK
157    ReadBurst            = FMC_SDRAM_RBURST_ENABLE               B
158    ReadPipeDelay        = FMC_SDRAM_RPIPE_DELAY_0               PP
159 
160    LoadToActiveDelay    = 2  -> 1     LLLL     TMRD
161    ExitSelfRefreshDelay = 6  -> 5     EEEE     TXSR
162    SelfRefreshTime      = 4  -> 3     SSSS     TRAS
163    RowCycleDelay        = 6  -> 5     RRRR     TRC
164    WriteRecoveryTime    = 2  -> 1     WWWW     TWR
165    RPDelay              = 2  -> 1     PPPP     TRP
166    RCDDelay             = 2  -> 1     CCCC     TRCD              */
167
168  FMC_Bank5_6_R->SDCR[0] = 0x00005965;  // 0000 0000 0000 0000 0101 1001 0110 0101  Bank 1
169                                        //                      PPB KKWL LNMM RRCC
170  FMC_Bank5_6_R->SDCR[1] = 0x00005965;  // 0000 0000 0000 0000 0101 1001 0110 0101  Bank 2  // CAS Latency = 2
171                                        //                            WL LNMM RRCC
172
173  FMC_Bank5_6_R->SDTR[0] = 0x00105000;  // 0000 0000 0001 0000 0101 0000 0000 0000  Bank 1  // Original,
174                                        //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 2 (s.o.)
175  FMC_Bank5_6_R->SDTR[1] = 0x01010351;  // 0000 0001 0000 0001 0000 0011 0101 0001  Bank 2
176                                        //      CCCC      WWWW      SSSS EEEE LLLL
177  #if 0
178  FMC_Bank5_6_R->SDTR[0] = 0x00206000;  // 0000 0000 0010 0000 0110 0000 0000 0000  Bank 1  // Original + 1 bei allen Werten,
179                                        //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 3 (s.o.)
180  FMC_Bank5_6_R->SDTR[1] = 0x02020462;  // 0000 0010 0000 0010 0000 0100 0110 0010  Bank 2
181                                        //      CCCC      WWWW      SSSS EEEE LLLL
182  #endif
183
184  #if 0
185  FMC_Bank5_6_R->SDTR[0] = 0x00209000;  // 0000 0000 0010 0000 1001 0000 0000 0000  Bank 1  // Versuch anhand ISSI-Datenblatt,
186                                        //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 3 (s.o.)
187  FMC_Bank5_6_R->SDTR[1] = 0x020306B1;  // 0000 0010 0000 0011 0000 0110 1011 0001  Bank 2
188                                        //      CCCC      WWWW      SSSS EEEE LLLL
189  #endif
190 
191  /* SDRAM initialization sequence */
192
193  /* Clock enable command */
194  FMC_Bank5_6_R->SDCMR = 0x00000009;
195  tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
196  while ((tmpreg != 0) && (timeout-- > 0))
197  {
198    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
199  }
200
201  /* Delay */
202  for (index=0; index<1000; index++);
203 
204  /* PALL command */
205  FMC_Bank5_6_R->SDCMR = 0x0000000A;   
206  timeout = 0xFFFF;
207  while ((tmpreg != 0) && (timeout-- > 0))
208  {
209    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
210  }
211 
212  FMC_Bank5_6_R->SDCMR = 0x000000EB;
213  timeout = 0xFFFF;
214  while ((tmpreg != 0) && (timeout-- > 0))
215  {
216    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
217  }
218
219  FMC_Bank5_6_R->SDCMR = 0x0004400C;
220  timeout = 0xFFFF;
221  while ((tmpreg != 0) && (timeout-- > 0))
222  {
223    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
224  }
225
226  /* Set refresh count */
227  tmpreg = FMC_Bank5_6_R->SDRTR;
228  FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
229
230  /* Disable write protection */
231  tmpreg = FMC_Bank5_6_R->SDCR[1];
232  FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
233
234  /* Configure FMC Bank Mapping */
235  FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
236
237   /* FMC controller Enable */
238  FMC_Bank1_R->BTCR[0] |= 0x80000000;
239 
240
241  /********** SDRAM only *************************************************************************/
242
243  #elif defined (DATA_IN_ExtSDRAM)
244
245  register uint32_t  tmpreg = 0, timeout = 0xFFFF;
246  register __IO      uint32_t index;
247
248  /*-- I/O Ports Configuration ------------------------------------------------------*/
249
250  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
251  RCC->AHB4ENR |= 0x000001F8;
252 
253  /* Connect PDx pins to FMC Alternate function */
254  GPIOD->AFR[0]  = 0x000000CC;
255  GPIOD->AFR[1]  = 0xCC000CCC;
256  /* Configure PDx pins in Alternate function mode */ 
257  GPIOD->MODER   = 0xAFEAFFFA;
258  /* Configure PDx pins speed to 100 MHz */ 
259  GPIOD->OSPEEDR = 0xF03F000F;
260  /* Configure PDx pins Output type to push-pull */ 
261  GPIOD->OTYPER  = 0x00000000;
262  /* Configure PDx pins in Pull-up */
263  GPIOD->PUPDR   = 0x50150005;
264   
265  /* Connect PEx pins to FMC Alternate function */
266  GPIOE->AFR[0]  = 0xC00000CC;
267  GPIOE->AFR[1]  = 0xCCCCCCCC;
268  /* Configure PEx pins in Alternate function mode */
269  GPIOE->MODER   = 0xAAAABFFA;
270  /* Configure PEx pins speed to 100 MHz */
271  GPIOE->OSPEEDR = 0xFFFFC00F;
272  /* Configure PEx pins Output type to push-pull */ 
273  GPIOE->OTYPER  = 0x00000000;
274  /* Configure PEx pins in Pull-up */
275  GPIOE->PUPDR   = 0x55554005;
276 
277  /* Connect PFx pins to FMC Alternate function */
278  GPIOF->AFR[0]  = 0x00CCCCCC;
279  GPIOF->AFR[1]  = 0xCCCCC000;
280  /* Configure PFx pins in Alternate function mode */   
281  GPIOF->MODER   = 0xAABFFAAA;
282  /* Configure PFx pins speed to 100 MHz */
283  GPIOF->OSPEEDR = 0xFFC00FFF;
284  /* Configure PFx pins Output type to push-pull */ 
285  GPIOF->OTYPER  = 0x00000000;
286  /* Configure PFx pins in Pull-up */
287  GPIOF->PUPDR   = 0x55400555;
288 
289  /* Connect PGx pins to FMC Alternate function */
290  GPIOG->AFR[0]  = 0x00CCCCCC;
291  GPIOG->AFR[1]  = 0xC000000C;
292  /* Configure PGx pins in Alternate function mode */
293  GPIOG->MODER   = 0xBFFEFAAA;
294 /* Configure PGx pins speed to 100 MHz */
295  GPIOG->OSPEEDR = 0xC0030FFF;
296  /* Configure PGx pins Output type to push-pull */ 
297  GPIOG->OTYPER  = 0x00000000;
298  /* Configure PGx pins in Pull-up */
299  GPIOG->PUPDR   = 0x40010555;
300 
301  /* Connect PHx pins to FMC Alternate function */
302  GPIOH->AFR[0]  = 0xCCC00000;
303  GPIOH->AFR[1]  = 0xCCCCCCCC;
304  /* Configure PHx pins in Alternate function mode */
305  GPIOH->MODER   = 0xAAAAABFF;
306  /* Configure PHx pins speed to 100 MHz */
307  GPIOH->OSPEEDR = 0xFFFFFC00;
308  /* Configure PHx pins Output type to push-pull */ 
309  GPIOH->OTYPER  = 0x00000000;
310  /* Configure PHx pins in Pull-up */
311  GPIOH->PUPDR   = 0x55555400;
312 
313  /* Connect PIx pins to FMC Alternate function */
314  GPIOI->AFR[0]  = 0xCCCCCCCC;
315  GPIOI->AFR[1]  = 0x00000CC0;
316  /* Configure PIx pins in Alternate function mode */
317  GPIOI->MODER   = 0xFFEBAAAA;
318  /* Configure PIx pins speed to 100 MHz */
319  GPIOI->OSPEEDR = 0x003CFFFF;
320  /* Configure PIx pins Output type to push-pull */ 
321  GPIOI->OTYPER  = 0x00000000;
322  /* Configure PIx pins in Pull-up */
323  GPIOI->PUPDR   = 0x00145555;
324 
325  /*-- FMC Configuration ------------------------------------------------------*/
326
327  /* Enable the FMC interface clock */
328  (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
329
330  /* SDRAM Timing and access interface configuration */
331
332  /*LoadToActiveDelay    = 2
333    ExitSelfRefreshDelay = 6
334    SelfRefreshTime      = 4
335    RowCycleDelay        = 6
336    WriteRecoveryTime    = 2
337    RPDelay              = 2
338    RCDDelay             = 2
339    SDBank               = FMC_SDRAM_BANK2
340    ColumnBitsNumber     = FMC_SDRAM_COLUMN_BITS_NUM_9
341    RowBitsNumber        = FMC_SDRAM_ROW_BITS_NUM_12
342    MemoryDataWidth      = FMC_SDRAM_MEM_BUS_WIDTH_32
343    InternalBankNumber   = FMC_SDRAM_INTERN_BANKS_NUM_4
344    CASLatency           = FMC_SDRAM_CAS_LATENCY_2
345    WriteProtection      = FMC_SDRAM_WRITE_PROTECTION_DISABLE
346    SDClockPeriod        = FMC_SDRAM_CLOCK_PERIOD_2
347    ReadBurst            = FMC_SDRAM_RBURST_ENABLE
348    ReadPipeDelay        = FMC_SDRAM_RPIPE_DELAY_0*/
349 
350  FMC_Bank5_6_R->SDCR[0] = 0x00001800;
351  FMC_Bank5_6_R->SDCR[1] = 0x00000165;
352  FMC_Bank5_6_R->SDTR[0] = 0x00105000;
353  FMC_Bank5_6_R->SDTR[1] = 0x01010351;
354
355  /* SDRAM initialization sequence */
356  /* Clock enable command */
357  FMC_Bank5_6_R->SDCMR = 0x00000009;
358  tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
359  while ((tmpreg != 0) && (timeout-- > 0))
360  {
361    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
362  }
363
364  /* Delay */
365  for (index=0; index<1000; index++);
366 
367  /* PALL command */
368    FMC_Bank5_6_R->SDCMR = 0x0000000A; 
369  timeout = 0xFFFF;
370  while ((tmpreg != 0) && (timeout-- > 0))
371  {
372    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
373  }
374 
375  FMC_Bank5_6_R->SDCMR = 0x000000EB;
376  timeout = 0xFFFF;
377  while ((tmpreg != 0) && (timeout-- > 0))
378  {
379    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
380  }
381
382  FMC_Bank5_6_R->SDCMR = 0x0004400C;
383  timeout = 0xFFFF;
384  while ((tmpreg != 0) && (timeout-- > 0))
385  {
386    tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
387  }
388  /* Set refresh count */
389  tmpreg = FMC_Bank5_6_R->SDRTR;
390  FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
391
392  /* Disable write protection */
393  tmpreg = FMC_Bank5_6_R->SDCR[1];
394  FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
395
396  /* FMC controller Enable */
397  FMC_Bank1_R->BTCR[0]  |= 0x80000000;
398
399  /********** SRAM only **************************************************************************/
400
401  #elif defined(DATA_IN_ExtSRAM)
402
403  /*-- I/O Ports Configuration -----------------------------------------------------*/
404
405  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
406  RCC->AHB4ENR |= 0x00000078;
407 
408  /* Connect PDx pins to FMC Alternate function */     
409  GPIOD->AFR[0]  = 0x00CC00CC;
410  GPIOD->AFR[1]  = 0xCCCCCCCC;
411  /* Configure PDx pins in Alternate function mode */ 
412  GPIOD->MODER   = 0xAAAAFABA;
413  /* Configure PDx pins speed to 100 MHz */ 
414  GPIOD->OSPEEDR = 0xFFFF0F0F;
415  /* Configure PDx pins Output type to push-pull */ 
416  GPIOD->OTYPER  = 0x00000000;
417  /* Configure PDx pins in Pull-up */
418  GPIOD->PUPDR   = 0x55550505;
419
420  /* Connect PEx pins to FMC Alternate function */
421  GPIOE->AFR[0]  = 0xC00CC0CC;
422  GPIOE->AFR[1]  = 0xCCCCCCCC;
423  /* Configure PEx pins in Alternate function mode */
424  GPIOE->MODER   = 0xAAAABEBA;
425  /* Configure PEx pins speed to 100 MHz */
426  GPIOE->OSPEEDR = 0xFFFFC3CF;
427  /* Configure PEx pins Output type to push-pull */ 
428  GPIOE->OTYPER  = 0x00000000;
429  /* Configure PEx pins in Pull-up */
430  GPIOE->PUPDR   = 0x55554145;
431
432  /* Connect PFx pins to FMC Alternate function */
433  GPIOF->AFR[0]  = 0x00CCCCCC;
434  GPIOF->AFR[1]  = 0xCCCC0000;
435  /* Configure PFx pins in Alternate function mode */   
436  GPIOF->MODER   = 0xAAFFFAAA;
437  /* Configure PFx pins speed to 100 MHz */
438  GPIOF->OSPEEDR = 0xFF000FFF;
439  /* Configure PFx pins Output type to push-pull */ 
440  GPIOF->OTYPER  = 0x00000000;
441  /* Configure PFx pins in Pull-up */
442  GPIOF->PUPDR   = 0x55000555;
443
444  /* Connect PGx pins to FMC Alternate function */
445  GPIOG->AFR[0]  = 0x00CCCCCC;
446  GPIOG->AFR[1]  = 0x00000C00;
447  /* Configure PGx pins in Alternate function mode */
448  GPIOG->MODER   = 0xFFEFFAAA;
449  /* Configure PGx pins speed to 100 MHz */
450  GPIOG->OSPEEDR = 0x00300FFF;
451  /* Configure PGx pins Output type to push-pull */ 
452  GPIOG->OTYPER  = 0x00000000;
453  /* Configure PGx pins in Pull-up */
454  GPIOG->PUPDR   = 0x00100555;
455 
456  /*-- FMC/FSMC Configuration --------------------------------------------------*/
457
458  /* Enable the FMC/FSMC interface clock */
459  (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
460
461  /* Configure and enable Bank1_SRAM2 */
462  FMC_Bank1_R->BTCR[4]  = 0x00001091;
463  FMC_Bank1_R->BTCR[5]  = 0x00110212;
464  FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF; 
465 
466  /* FMC controller Enable */
467  FMC_Bank1_R->BTCR[0] |= 0x80000000; 
468
469  #endif /* DATA_IN_ExtSRAM */
470 
471  (void)(tmp);
472
473}
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