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source: rtems/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c @ 1a4e78b3

Last change on this file since 1a4e78b3 was 1a4e78b3, checked in by Karel Gardas <karel@…>, on 03/09/23 at 13:15:53

bsps/stm32h7: fix propagation of configured HSE freq. value into the code

Sponsored-By: Precidata

Property mode set to 100644

File size: 28.1 KB

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1	/* SPDX-License-Identifier: BSD-3-Clause */
2	/**
3	******************************************************************************
4	* @file system_stm32h7xx.c
5	* @author MCD Application Team
6	* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
7	*
8	* This file provides two functions and one global variable to be called from
9	* user application:
10	* - SystemInit(): This function is called at startup just after reset and
11	* before branch to main program. This call is made inside
12	* the "startup_stm32h7xx.s" file.
13	*
14	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
15	* by the user application to setup the SysTick
16	* timer or configure other parameters.
17	*
18	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
19	* be called whenever the core clock is changed
20	* during program execution.
21	*
22	*
23	******************************************************************************
24	* @attention
25	*
26	* Copyright (c) 2019 STMicroelectronics.
27	* All rights reserved.
28	*
29	* This software is licensed under terms that can be found in the LICENSE file
30	* in the root directory of this software component.
31	* If no LICENSE file comes with this software, it is provided AS-IS.
32	*
33	******************************************************************************
34	*/
35	/*
36	* RTEMS committer clarification comment on license above:
37	*
38	* This file comes from STM32CubeH7 project from its Projects
39	* subdirectory. There is Templates subdirectory per every supported
40	* BSP there. The Templates contains the file. In our case the file is
41	* here:
42	* https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Projects/STM32H747I-EVAL/Templates/BootCM4_CM7/Common/Src/system_stm32h7xx.c
43	*
44	* When we go up in the directory tree starting from the file, we find
45	* out that the "root directory" in the sense of license claim above is Templates
46	* directory here:
47	* https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/STM32H747I-EVAL/Templates
48	*
49	* This directory contains LICENSE.md file with a following license text:
50	*
51	* Copyright 2019 STMicroelectronics.
52	* All rights reserved.
53	*
54	* Redistribution and use in source and binary forms, with or without modification,
55	* are permitted provided that the following conditions are met:
56	*
57	* 1. Redistributions of source code must retain the above copyright notice, this
58	* list of conditions and the following disclaimer.
59	*
60	* 2. Redistributions in binary form must reproduce the above copyright notice,
61	* this list of conditions and the following disclaimer in the documentation and/or
62	* other materials provided with the distribution.
63	*
64	* 3. Neither the name of the copyright holder nor the names of its contributors
65	* may be used to endorse or promote products derived from this software without
66	* specific prior written permission.
67	*
68	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
69	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
70	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
71	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
72	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
73	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
74	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
75	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
77	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78	*/
79
80	/** @addtogroup CMSIS
81	* @{
82	*/
83
84	/** @addtogroup stm32h7xx_system
85	* @{
86	*/
87
88	/** @addtogroup STM32H7xx_System_Private_Includes
89	* @{
90	*/
91
92	#include "stm32h7xx.h"
93	#include <math.h>
94	#ifdef __rtems__
95	#include <bsp/linker-symbols.h>
96	#include <bspopts.h>
97
98	#define HSE_VALUE STM32H7_HSE_FREQUENCY
99
100	#endif /* __rtems__ */
101	#if !defined (HSE_VALUE)
102	#define HSE_VALUE ((uint32_t)25000000) /!< Value of the External oscillator in Hz /
103	#endif /* HSE_VALUE */
104
105	#if !defined (CSI_VALUE)
106	#define CSI_VALUE ((uint32_t)4000000) /!< Value of the Internal oscillator in Hz/
107	#endif /* CSI_VALUE */
108
109	#if !defined (HSI_VALUE)
110	#define HSI_VALUE ((uint32_t)64000000) /!< Value of the Internal oscillator in Hz/
111	#endif /* HSI_VALUE */
112
113	/**
114	* @}
115	*/
116
117	/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
118	* @{
119	*/
120
121	/**
122	* @}
123	*/
124
125	/** @addtogroup STM32H7xx_System_Private_Defines
126	* @{
127	*/
128
129	/*********************** Miscellaneous Configuration **********************/
130	/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
131	on EVAL board as data memory */
132	#define DATA_IN_ExtSRAM
133	#define DATA_IN_ExtSDRAM
134
135	/*!< Uncomment the following line if you need to relocate your vector Table in
136	Internal SRAM. */
137	/* #define VECT_TAB_SRAM */
138	#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
139	This value must be a multiple of 0x200. */
140	/******************************************************************************/
141
142	/**
143	* @}
144	*/
145
146	/** @addtogroup STM32H7xx_System_Private_Macros
147	* @{
148	*/
149
150	/**
151	* @}
152	*/
153
154	/** @addtogroup STM32H7xx_System_Private_Variables
155	* @{
156	*/
157	/* This variable is updated in three ways:
158	1) by calling CMSIS function SystemCoreClockUpdate()
159	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
160	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
161	Note: If you use this function to configure the system clock; then there
162	is no need to call the 2 first functions listed above, since SystemCoreClock
163	variable is updated automatically.
164	*/
165	#ifndef __rtems__
166	uint32_t SystemCoreClock = 64000000;
167	uint32_t SystemD2Clock = 64000000;
168	#else /* __rtems__ */
169	RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
170	RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
171	#endif /* __rtems__ */
172	const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
173
174	/**
175	* @}
176	*/
177
178	/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
179	* @{
180	*/
181	#ifndef __rtems__
182	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
183	static void SystemInit_ExtMemCtl(void);
184	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
185	#endif /* __rtems__ */
186
187	/**
188	* @}
189	*/
190
191	/** @addtogroup STM32H7xx_System_Private_Functions
192	* @{
193	*/
194
195	/**
196	* @brief Setup the microcontroller system
197	* Initialize the FPU setting, vector table location and External memory
198	* configuration.
199	* @param None
200	* @retval None
201	*/
202	void SystemInit (void)
203	{
204	/* FPU settings ------------------------------------------------------------*/
205	#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
206	SCB->CPACR \|= ((3UL << (102))\|(3UL << (112))); /* set CP10 and CP11 Full Access */
207	#endif
208
209	/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
210	detectable by the CPU after a WFI/WFE instruction.*/
211	SCB->SCR \|= SCB_SCR_SEVONPEND_Msk;
212
213	#ifdef CORE_CM7
214	/* Reset the RCC clock configuration to the default reset state ------------*/
215	/* Set HSION bit */
216	RCC->CR \|= RCC_CR_HSION;
217
218	/* Reset CFGR register */
219	RCC->CFGR = 0x00000000;
220
221	/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
222	RCC->CR &= 0xEAF6ED7FU;
223
224	/* Reset D1CFGR register */
225	RCC->D1CFGR = 0x00000000;
226
227	/* Reset D2CFGR register */
228	RCC->D2CFGR = 0x00000000;
229
230	/* Reset D3CFGR register */
231	RCC->D3CFGR = 0x00000000;
232
233	/* Reset PLLCKSELR register */
234	RCC->PLLCKSELR = 0x00000000;
235
236	/* Reset PLLCFGR register */
237	RCC->PLLCFGR = 0x00000000;
238	/* Reset PLL1DIVR register */
239	RCC->PLL1DIVR = 0x00000000;
240	/* Reset PLL1FRACR register */
241	RCC->PLL1FRACR = 0x00000000;
242
243	/* Reset PLL2DIVR register */
244	RCC->PLL2DIVR = 0x00000000;
245
246	/* Reset PLL2FRACR register */
247
248	RCC->PLL2FRACR = 0x00000000;
249	/* Reset PLL3DIVR register */
250	RCC->PLL3DIVR = 0x00000000;
251
252	/* Reset PLL3FRACR register */
253	RCC->PLL3FRACR = 0x00000000;
254
255	/* Reset HSEBYP bit */
256	RCC->CR &= 0xFFFBFFFFU;
257
258	/* Disable all interrupts */
259	RCC->CIER = 0x00000000;
260
261	/* Enable CortexM7 HSEM EXTI line (line 78)*/
262	EXTI_D2->EMR3 \|= 0x4000UL;
263
264	/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
265	if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
266	{
267	/* if stm32h7 revY*/
268	/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
269	((__IO uint32_t)0x51008108) = 0x00000001U;
270	}
271
272
273	/*
274	* Disable the FMC bank1 (enabled after reset).
275	* This, prevents CPU speculation access on this bank which blocks the use of FMC during
276	* 24us. During this time the others FMC master (such as LTDC) cannot use it!
277	*/
278	FMC_Bank1_R->BTCR[0] = 0x000030D2;
279
280	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
281	SystemInit_ExtMemCtl();
282	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
283
284	#endif /* CORE_CM7*/
285
286	#ifndef __rtems__
287	#ifdef CORE_CM4
288
289	/* Configure the Vector Table location add offset address ------------------*/
290	#ifdef VECT_TAB_SRAM
291	SCB->VTOR = D2_AXISRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
292	#else
293	SCB->VTOR = FLASH_BANK2_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
294	#endif
295
296	#else
297	#ifdef CORE_CM7
298
299	/* Configure the Vector Table location add offset address ------------------*/
300	#ifdef VECT_TAB_SRAM
301	SCB->VTOR = D1_AXISRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
302	#else
303	SCB->VTOR = FLASH_BANK1_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
304	#endif
305
306	#else
307	#error Please #define CORE_CM4 or CORE_CM7
308	#endif
309	#endif
310
311	#else /* __rtems__ */
312	SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
313	#endif /* __rtems__ */
314
315	}
316
317	/**
318	* @brief Update SystemCoreClock variable according to Clock Register Values.
319	* The SystemCoreClock variable contains the core clock , it can
320	* be used by the user application to setup the SysTick timer or configure
321	* other parameters.
322	*
323	* @note Each time the core clock changes, this function must be called
324	* to update SystemCoreClock variable value. Otherwise, any configuration
325	* based on this variable will be incorrect.
326	*
327	* @note - The system frequency computed by this function is not the real
328	* frequency in the chip. It is calculated based on the predefined
329	* constant and the selected clock source:
330	*
331	* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
332	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
333	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
334	* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
335	* HSI_VALUE() or HSE_VALUE(*) multiplied/divided by the PLL factors.
336	*
337	* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
338	* 4 MHz) but the real value may vary depending on the variations
339	* in voltage and temperature.
340	* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
341	* 64 MHz) but the real value may vary depending on the variations
342	* in voltage and temperature.
343	*
344	* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
345	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
346	* frequency of the crystal used. Otherwise, this function may
347	* have wrong result.
348	*
349	* - The result of this function could be not correct when using fractional
350	* value for HSE crystal.
351	* @param None
352	* @retval None
353	*/
354	void SystemCoreClockUpdate (void)
355	{
356	uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
357	uint32_t common_system_clock;
358	float_t fracn1, pllvco;
359
360	/* Get SYSCLK source -------------------------------------------------------*/
361
362	switch (RCC->CFGR & RCC_CFGR_SWS)
363	{
364	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
365	common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
366	break;
367
368	case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
369	common_system_clock = CSI_VALUE;
370	break;
371
372	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
373	common_system_clock = HSE_VALUE;
374	break;
375
376	case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
377
378	/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
379	SYSCLK = PLL_VCO / PLLR
380	*/
381	pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
382	pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
383	pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
384	fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
385
386	if (pllm != 0U)
387	{
388	switch (pllsource)
389	{
390	case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
391
392	hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
393	pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
394
395	break;
396
397	case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
398	pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
399	break;
400
401	case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
402	pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
403	break;
404
405	default:
406	pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
407	break;
408	}
409	pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
410	common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
411	}
412	else
413	{
414	common_system_clock = 0U;
415	}
416	break;
417
418	default:
419	common_system_clock = CSI_VALUE;
420	break;
421	}
422
423	/* Compute SystemClock frequency --------------------------------------------------*/
424	tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
425
426	/* common_system_clock frequency : CM7 CPU frequency */
427	common_system_clock >>= tmp;
428
429	/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
430	SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
431
432	#if defined(DUAL_CORE) && defined(CORE_CM4)
433	SystemCoreClock = SystemD2Clock;
434	#else
435	SystemCoreClock = common_system_clock;
436	#endif /* DUAL_CORE && CORE_CM4 */
437	}
438	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
439	/**
440	* @brief Setup the external memory controller.
441	* Called in startup_stm32h7xx.s before jump to main.
442	* This function configures the external memories (SRAM/SDRAM)
443	* This SRAM/SDRAM will be used as program data memory (including heap and stack).
444	* @param None
445	* @retval None
446	*/
447	void SystemInit_ExtMemCtl(void)
448	{
449	__IO uint32_t tmp = 0;
450
451	#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
452	register uint32_t tmpreg = 0, timeout = 0xFFFF;
453	register __IO uint32_t index;
454
455	/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
456	clock */
457	RCC->AHB4ENR \|= 0x000001F8;
458
459	/* Delay after an RCC peripheral clock enabling */
460	tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
461
462	/* Connect PDx pins to FMC Alternate function */
463	GPIOD->AFR[0] = 0x00CC00CC;
464	GPIOD->AFR[1] = 0xCCCCCCCC;
465	/* Configure PDx pins in Alternate function mode */
466	GPIOD->MODER = 0xAAAAFAFA;
467	/* Configure PDx pins speed to 100 MHz */
468	GPIOD->OSPEEDR = 0xFFFF0F0F;
469	/* Configure PDx pins Output type to push-pull */
470	GPIOD->OTYPER = 0x00000000;
471	/* Configure PDx pins in Pull-up */
472	GPIOD->PUPDR = 0x55550505;
473
474	/* Connect PEx pins to FMC Alternate function */
475	GPIOE->AFR[0] = 0xC00CC0CC;
476	GPIOE->AFR[1] = 0xCCCCCCCC;
477	/* Configure PEx pins in Alternate function mode */
478	GPIOE->MODER = 0xAAAABEBA;
479	/* Configure PEx pins speed to 100 MHz */
480	GPIOE->OSPEEDR = 0xFFFFC3CF;
481	/* Configure PEx pins Output type to push-pull */
482	GPIOE->OTYPER = 0x00000000;
483	/* Configure PEx pins in Pull-up */
484	GPIOE->PUPDR = 0x55554145;
485
486	/* Connect PFx pins to FMC Alternate function */
487	GPIOF->AFR[0] = 0x00CCCCCC;
488	GPIOF->AFR[1] = 0xCCCCC000;
489	/* Configure PFx pins in Alternate function mode */
490	GPIOF->MODER = 0xAABFFAAA;
491	/* Configure PFx pins speed to 100 MHz */
492	GPIOF->OSPEEDR = 0xFFC00FFF;
493	/* Configure PFx pins Output type to push-pull */
494	GPIOF->OTYPER = 0x00000000;
495	/* Configure PFx pins in Pull-up */
496	GPIOF->PUPDR = 0x55400555;
497
498	/* Connect PGx pins to FMC Alternate function */
499	GPIOG->AFR[0] = 0x00CCCCCC;
500	GPIOG->AFR[1] = 0xC0000C0C;
501	/* Configure PGx pins in Alternate function mode */
502	GPIOG->MODER = 0xBFEEFAAA;
503	/* Configure PGx pins speed to 100 MHz */
504	GPIOG->OSPEEDR = 0xC0330FFF;
505	/* Configure PGx pins Output type to push-pull */
506	GPIOG->OTYPER = 0x00000000;
507	/* Configure PGx pins in Pull-up */
508	GPIOG->PUPDR = 0x40110555;
509
510	/* Connect PHx pins to FMC Alternate function */
511	GPIOH->AFR[0] = 0xCCC00000;
512	GPIOH->AFR[1] = 0xCCCCCCCC;
513	/* Configure PHx pins in Alternate function mode */
514	GPIOH->MODER = 0xAAAAABFF;
515	/* Configure PHx pins speed to 100 MHz */
516	GPIOH->OSPEEDR = 0xFFFFFC00;
517	/* Configure PHx pins Output type to push-pull */
518	GPIOH->OTYPER = 0x00000000;
519	/* Configure PHx pins in Pull-up */
520	GPIOH->PUPDR = 0x55555400;
521
522	/* Connect PIx pins to FMC Alternate function */
523	GPIOI->AFR[0] = 0xCCCCCCCC;
524	GPIOI->AFR[1] = 0x00000CC0;
525	/* Configure PIx pins in Alternate function mode */
526	GPIOI->MODER = 0xFFEBAAAA;
527	/* Configure PIx pins speed to 100 MHz */
528	GPIOI->OSPEEDR = 0x003CFFFF;
529	/* Configure PIx pins Output type to push-pull */
530	GPIOI->OTYPER = 0x00000000;
531	/* Configure PIx pins in Pull-up */
532	GPIOI->PUPDR = 0x00145555;
533
534	/* Enable the FMC/FSMC interface clock */
535	(RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN));
536
537	/* Configure and enable Bank1_SRAM2 */
538	FMC_Bank1_R->BTCR[4] = 0x00001091;
539	FMC_Bank1_R->BTCR[5] = 0x00110212;
540	FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
541
542	/SDRAM Timing and access interface configuration/
543	/*LoadToActiveDelay = 2
544	ExitSelfRefreshDelay = 6
545	SelfRefreshTime = 4
546	RowCycleDelay = 6
547	WriteRecoveryTime = 2
548	RPDelay = 2
549	RCDDelay = 2
550	SDBank = FMC_SDRAM_BANK2
551	ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
552	RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
553	MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
554	InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
555	CASLatency = FMC_SDRAM_CAS_LATENCY_2
556	WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
557	SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
558	ReadBurst = FMC_SDRAM_RBURST_ENABLE
559	ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
560
561	FMC_Bank5_6_R->SDCR[0] = 0x00001800;
562	FMC_Bank5_6_R->SDCR[1] = 0x00000165;
563	FMC_Bank5_6_R->SDTR[0] = 0x00105000;
564	FMC_Bank5_6_R->SDTR[1] = 0x01010351;
565
566	/* SDRAM initialization sequence */
567	/* Clock enable command */
568	FMC_Bank5_6_R->SDCMR = 0x00000009;
569	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
570	while((tmpreg != 0) && (timeout-- > 0))
571	{
572	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
573	}
574
575	/* Delay */
576	for (index = 0; index<1000; index++);
577
578	/* PALL command */
579	FMC_Bank5_6_R->SDCMR = 0x0000000A;
580	timeout = 0xFFFF;
581	while((tmpreg != 0) && (timeout-- > 0))
582	{
583	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
584	}
585
586	FMC_Bank5_6_R->SDCMR = 0x000000EB;
587	timeout = 0xFFFF;
588	while((tmpreg != 0) && (timeout-- > 0))
589	{
590	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
591	}
592
593	FMC_Bank5_6_R->SDCMR = 0x0004400C;
594	timeout = 0xFFFF;
595	while((tmpreg != 0) && (timeout-- > 0))
596	{
597	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
598	}
599	/* Set refresh count */
600	tmpreg = FMC_Bank5_6_R->SDRTR;
601	FMC_Bank5_6_R->SDRTR = (tmpreg \| (0x00000603<<1));
602
603	/* Disable write protection */
604	tmpreg = FMC_Bank5_6_R->SDCR[1];
605	FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
606
607	/FMC controller Enable/
608	FMC_Bank1_R->BTCR[0] \|= 0x80000000;
609
610	#elif defined (DATA_IN_ExtSDRAM)
611	register uint32_t tmpreg = 0, timeout = 0xFFFF;
612	register __IO uint32_t index;
613
614	/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
615	clock */
616	RCC->AHB4ENR \|= 0x000001F8;
617
618	/* Connect PDx pins to FMC Alternate function */
619	GPIOD->AFR[0] = 0x000000CC;
620	GPIOD->AFR[1] = 0xCC000CCC;
621	/* Configure PDx pins in Alternate function mode */
622	GPIOD->MODER = 0xAFEAFFFA;
623	/* Configure PDx pins speed to 100 MHz */
624	GPIOD->OSPEEDR = 0xF03F000F;
625	/* Configure PDx pins Output type to push-pull */
626	GPIOD->OTYPER = 0x00000000;
627	/* Configure PDx pins in Pull-up */
628	GPIOD->PUPDR = 0x50150005;
629
630	/* Connect PEx pins to FMC Alternate function */
631	GPIOE->AFR[0] = 0xC00000CC;
632	GPIOE->AFR[1] = 0xCCCCCCCC;
633	/* Configure PEx pins in Alternate function mode */
634	GPIOE->MODER = 0xAAAABFFA;
635	/* Configure PEx pins speed to 100 MHz */
636	GPIOE->OSPEEDR = 0xFFFFC00F;
637	/* Configure PEx pins Output type to push-pull */
638	GPIOE->OTYPER = 0x00000000;
639	/* Configure PEx pins in Pull-up */
640	GPIOE->PUPDR = 0x55554005;
641
642	/* Connect PFx pins to FMC Alternate function */
643	GPIOF->AFR[0] = 0x00CCCCCC;
644	GPIOF->AFR[1] = 0xCCCCC000;
645	/* Configure PFx pins in Alternate function mode */
646	GPIOF->MODER = 0xAABFFAAA;
647	/* Configure PFx pins speed to 100 MHz */
648	GPIOF->OSPEEDR = 0xFFC00FFF;
649	/* Configure PFx pins Output type to push-pull */
650	GPIOF->OTYPER = 0x00000000;
651	/* Configure PFx pins in Pull-up */
652	GPIOF->PUPDR = 0x55400555;
653
654	/* Connect PGx pins to FMC Alternate function */
655	GPIOG->AFR[0] = 0x00CCCCCC;
656	GPIOG->AFR[1] = 0xC000000C;
657	/* Configure PGx pins in Alternate function mode */
658	GPIOG->MODER = 0xBFFEFAAA;
659	/* Configure PGx pins speed to 100 MHz */
660	GPIOG->OSPEEDR = 0xC0030FFF;
661	/* Configure PGx pins Output type to push-pull */
662	GPIOG->OTYPER = 0x00000000;
663	/* Configure PGx pins in Pull-up */
664	GPIOG->PUPDR = 0x40010555;
665
666	/* Connect PHx pins to FMC Alternate function */
667	GPIOH->AFR[0] = 0xCCC00000;
668	GPIOH->AFR[1] = 0xCCCCCCCC;
669	/* Configure PHx pins in Alternate function mode */
670	GPIOH->MODER = 0xAAAAABFF;
671	/* Configure PHx pins speed to 100 MHz */
672	GPIOH->OSPEEDR = 0xFFFFFC00;
673	/* Configure PHx pins Output type to push-pull */
674	GPIOH->OTYPER = 0x00000000;
675	/* Configure PHx pins in Pull-up */
676	GPIOH->PUPDR = 0x55555400;
677
678	/* Connect PIx pins to FMC Alternate function */
679	GPIOI->AFR[0] = 0xCCCCCCCC;
680	GPIOI->AFR[1] = 0x00000CC0;
681	/* Configure PIx pins in Alternate function mode */
682	GPIOI->MODER = 0xFFEBAAAA;
683	/* Configure PIx pins speed to 100 MHz */
684	GPIOI->OSPEEDR = 0x003CFFFF;
685	/* Configure PIx pins Output type to push-pull */
686	GPIOI->OTYPER = 0x00000000;
687	/* Configure PIx pins in Pull-up */
688	GPIOI->PUPDR = 0x00145555;
689
690	/-- FMC Configuration ------------------------------------------------------/
691	/* Enable the FMC interface clock */
692	(RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN));
693	/SDRAM Timing and access interface configuration/
694	/*LoadToActiveDelay = 2
695	ExitSelfRefreshDelay = 6
696	SelfRefreshTime = 4
697	RowCycleDelay = 6
698	WriteRecoveryTime = 2
699	RPDelay = 2
700	RCDDelay = 2
701	SDBank = FMC_SDRAM_BANK2
702	ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
703	RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
704	MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
705	InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
706	CASLatency = FMC_SDRAM_CAS_LATENCY_2
707	WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
708	SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
709	ReadBurst = FMC_SDRAM_RBURST_ENABLE
710	ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
711
712	FMC_Bank5_6_R->SDCR[0] = 0x00001800;
713	FMC_Bank5_6_R->SDCR[1] = 0x00000165;
714	FMC_Bank5_6_R->SDTR[0] = 0x00105000;
715	FMC_Bank5_6_R->SDTR[1] = 0x01010351;
716
717	/* SDRAM initialization sequence */
718	/* Clock enable command */
719	FMC_Bank5_6_R->SDCMR = 0x00000009;
720	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
721	while((tmpreg != 0) && (timeout-- > 0))
722	{
723	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
724	}
725
726	/* Delay */
727	for (index = 0; index<1000; index++);
728
729	/* PALL command */
730	FMC_Bank5_6_R->SDCMR = 0x0000000A;
731	timeout = 0xFFFF;
732	while((tmpreg != 0) && (timeout-- > 0))
733	{
734	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
735	}
736
737	FMC_Bank5_6_R->SDCMR = 0x000000EB;
738	timeout = 0xFFFF;
739	while((tmpreg != 0) && (timeout-- > 0))
740	{
741	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
742	}
743
744	FMC_Bank5_6_R->SDCMR = 0x0004400C;
745	timeout = 0xFFFF;
746	while((tmpreg != 0) && (timeout-- > 0))
747	{
748	tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
749	}
750	/* Set refresh count */
751	tmpreg = FMC_Bank5_6_R->SDRTR;
752	FMC_Bank5_6_R->SDRTR = (tmpreg \| (0x00000603<<1));
753
754	/* Disable write protection */
755	tmpreg = FMC_Bank5_6_R->SDCR[1];
756	FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
757
758	/FMC controller Enable/
759	FMC_Bank1_R->BTCR[0] \|= 0x80000000;
760
761	#elif defined(DATA_IN_ExtSRAM)
762	/-- GPIOs Configuration -----------------------------------------------------/
763	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
764	RCC->AHB4ENR \|= 0x00000078;
765
766	/* Connect PDx pins to FMC Alternate function */
767	GPIOD->AFR[0] = 0x00CC00CC;
768	GPIOD->AFR[1] = 0xCCCCCCCC;
769	/* Configure PDx pins in Alternate function mode */
770	GPIOD->MODER = 0xAAAAFABA;
771	/* Configure PDx pins speed to 100 MHz */
772	GPIOD->OSPEEDR = 0xFFFF0F0F;
773	/* Configure PDx pins Output type to push-pull */
774	GPIOD->OTYPER = 0x00000000;
775	/* Configure PDx pins in Pull-up */
776	GPIOD->PUPDR = 0x55550505;
777
778	/* Connect PEx pins to FMC Alternate function */
779	GPIOE->AFR[0] = 0xC00CC0CC;
780	GPIOE->AFR[1] = 0xCCCCCCCC;
781	/* Configure PEx pins in Alternate function mode */
782	GPIOE->MODER = 0xAAAABEBA;
783	/* Configure PEx pins speed to 100 MHz */
784	GPIOE->OSPEEDR = 0xFFFFC3CF;
785	/* Configure PEx pins Output type to push-pull */
786	GPIOE->OTYPER = 0x00000000;
787	/* Configure PEx pins in Pull-up */
788	GPIOE->PUPDR = 0x55554145;
789
790	/* Connect PFx pins to FMC Alternate function */
791	GPIOF->AFR[0] = 0x00CCCCCC;
792	GPIOF->AFR[1] = 0xCCCC0000;
793	/* Configure PFx pins in Alternate function mode */
794	GPIOF->MODER = 0xAAFFFAAA;
795	/* Configure PFx pins speed to 100 MHz */
796	GPIOF->OSPEEDR = 0xFF000FFF;
797	/* Configure PFx pins Output type to push-pull */
798	GPIOF->OTYPER = 0x00000000;
799	/* Configure PFx pins in Pull-up */
800	GPIOF->PUPDR = 0x55000555;
801
802	/* Connect PGx pins to FMC Alternate function */
803	GPIOG->AFR[0] = 0x00CCCCCC;
804	GPIOG->AFR[1] = 0x00000C00;
805	/* Configure PGx pins in Alternate function mode */
806	GPIOG->MODER = 0xFFEFFAAA;
807	/* Configure PGx pins speed to 100 MHz */
808	GPIOG->OSPEEDR = 0x00300FFF;
809	/* Configure PGx pins Output type to push-pull */
810	GPIOG->OTYPER = 0x00000000;
811	/* Configure PGx pins in Pull-up */
812	GPIOG->PUPDR = 0x00100555;
813
814	/-- FMC/FSMC Configuration --------------------------------------------------/
815	/* Enable the FMC/FSMC interface clock */
816	(RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN));
817
818	/* Configure and enable Bank1_SRAM2 */
819	FMC_Bank1_R->BTCR[4] = 0x00001091;
820	FMC_Bank1_R->BTCR[5] = 0x00110212;
821	FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
822
823	/FMC controller Enable/
824	FMC_Bank1_R->BTCR[0] \|= 0x80000000;
825
826	#endif /* DATA_IN_ExtSRAM */
827
828	(void)(tmp);
829	}
830	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
831
832
833	/**
834	* @}
835	*/
836
837	/**
838	* @}
839	*/
840
841	/**
842	* @}
843	*/

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