source: rtems/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/system_stm32h7xx.c @ f8a9a47d

Last change on this file since f8a9a47d was f8a9a47d, checked in by Karel Gardas <karel@…>, on 05/15/22 at 20:10:42

bsp/stm32h7: copy system files to stm32h743i-eval board directory

Also adjust BSP spec file to make it buildable with board files.

Sponsored-By: Precidata
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File size: 13.3 KB
Line 
1/**
2  ******************************************************************************
3  * @file    system_stm32h7xx.c
4  * @author  MCD Application Team
5  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
6  *
7  *   This file provides two functions and one global variable to be called from
8  *   user application:
9  *      - SystemInit(): This function is called at startup just after reset and
10  *                      before branch to main program. This call is made inside
11  *                      the "startup_stm32h7xx.s" file.
12  *
13  *      - SystemCoreClock variable: Contains the core clock, it can be used
14  *                                  by the user application to setup the SysTick
15  *                                  timer or configure other parameters.
16  *
17  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18  *                                 be called whenever the core clock is changed
19  *                                 during program execution.
20  *
21  *
22  ******************************************************************************
23  * @attention
24  *
25  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26  * All rights reserved.</center></h2>
27  *
28  * This software component is licensed by ST under BSD 3-Clause license,
29  * the "License"; You may not use this file except in compliance with the
30  * License. You may obtain a copy of the License at:
31  *                        opensource.org/licenses/BSD-3-Clause
32  *
33  ******************************************************************************
34  */
35
36/** @addtogroup CMSIS
37  * @{
38  */
39
40/** @addtogroup stm32h7xx_system
41  * @{
42  */
43
44/** @addtogroup STM32H7xx_System_Private_Includes
45  * @{
46  */
47
48#include "stm32h7xx.h"
49#include <math.h>
50#ifdef __rtems__
51#include <bsp/linker-symbols.h>
52#endif /* __rtems__ */
53#if !defined  (HSE_VALUE)
54#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
55#endif /* HSE_VALUE */
56
57#if !defined  (CSI_VALUE)
58  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
59#endif /* CSI_VALUE */
60
61#if !defined  (HSI_VALUE)
62  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
63#endif /* HSI_VALUE */
64
65
66/**
67  * @}
68  */
69
70/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
71  * @{
72  */
73
74/**
75  * @}
76  */
77
78/** @addtogroup STM32H7xx_System_Private_Defines
79  * @{
80  */
81
82/************************* Miscellaneous Configuration ************************/
83/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
84/* #define DATA_IN_D2_SRAM */
85
86/*!< Uncomment the following line if you need to relocate your vector Table in
87     Internal SRAM. */
88/* #define VECT_TAB_SRAM */
89#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
90                                      This value must be a multiple of 0x200. */
91/******************************************************************************/
92
93/**
94  * @}
95  */
96
97/** @addtogroup STM32H7xx_System_Private_Macros
98  * @{
99  */
100
101/**
102  * @}
103  */
104
105/** @addtogroup STM32H7xx_System_Private_Variables
106  * @{
107  */
108  /* This variable is updated in three ways:
109      1) by calling CMSIS function SystemCoreClockUpdate()
110      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
111      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
112         Note: If you use this function to configure the system clock; then there
113               is no need to call the 2 first functions listed above, since SystemCoreClock
114               variable is updated automatically.
115  */
116#ifndef __rtems__
117  uint32_t SystemCoreClock = 64000000;
118  uint32_t SystemD2Clock = 64000000;
119#else /* __rtems__ */
120  RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
121  RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
122#endif /* __rtems__ */
123  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
124
125/**
126  * @}
127  */
128
129/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
130  * @{
131  */
132
133/**
134  * @}
135  */
136
137/** @addtogroup STM32H7xx_System_Private_Functions
138  * @{
139  */
140
141/**
142  * @brief  Setup the microcontroller system
143  *         Initialize the FPU setting and  vector table location
144  *         configuration.
145  * @param  None
146  * @retval None
147  */
148void SystemInit (void)
149{
150#if defined (DATA_IN_D2_SRAM)
151 __IO uint32_t tmpreg;
152#endif /* DATA_IN_D2_SRAM */
153
154  /* FPU settings ------------------------------------------------------------*/
155  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
156    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
157  #endif
158  /* Reset the RCC clock configuration to the default reset state ------------*/
159  /* Set HSION bit */
160  RCC->CR |= RCC_CR_HSION;
161
162  /* Reset CFGR register */
163  RCC->CFGR = 0x00000000;
164
165  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
166  RCC->CR &= 0xEAF6ED7FU;
167
168#if defined(D3_SRAM_BASE)
169  /* Reset D1CFGR register */
170  RCC->D1CFGR = 0x00000000;
171
172  /* Reset D2CFGR register */
173  RCC->D2CFGR = 0x00000000;
174
175  /* Reset D3CFGR register */
176  RCC->D3CFGR = 0x00000000;
177#else
178  /* Reset CDCFGR1 register */
179  RCC->CDCFGR1 = 0x00000000;
180
181  /* Reset CDCFGR2 register */
182  RCC->CDCFGR2 = 0x00000000;
183
184  /* Reset SRDCFGR register */
185  RCC->SRDCFGR = 0x00000000;
186#endif
187  /* Reset PLLCKSELR register */
188  RCC->PLLCKSELR = 0x00000000;
189
190  /* Reset PLLCFGR register */
191  RCC->PLLCFGR = 0x00000000;
192  /* Reset PLL1DIVR register */
193  RCC->PLL1DIVR = 0x00000000;
194  /* Reset PLL1FRACR register */
195  RCC->PLL1FRACR = 0x00000000;
196
197  /* Reset PLL2DIVR register */
198  RCC->PLL2DIVR = 0x00000000;
199
200  /* Reset PLL2FRACR register */
201
202  RCC->PLL2FRACR = 0x00000000;
203  /* Reset PLL3DIVR register */
204  RCC->PLL3DIVR = 0x00000000;
205
206  /* Reset PLL3FRACR register */
207  RCC->PLL3FRACR = 0x00000000;
208
209  /* Reset HSEBYP bit */
210  RCC->CR &= 0xFFFBFFFFU;
211
212  /* Disable all interrupts */
213  RCC->CIER = 0x00000000;
214
215#if (STM32H7_DEV_ID == 0x450UL)
216  /* dual core CM7 or single core line */
217  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
218  {
219    /* if stm32h7 revY*/
220    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
221    *((__IO uint32_t*)0x51008108) = 0x000000001U;
222  }
223#endif
224
225#ifndef __rtems__
226#if defined (DATA_IN_D2_SRAM)
227  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
228#if defined(RCC_AHB2ENR_D2SRAM3EN)
229  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
230#elif defined(RCC_AHB2ENR_D2SRAM2EN)
231  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
232#else
233  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
234#endif /* RCC_AHB2ENR_D2SRAM3EN */
235
236  tmpreg = RCC->AHB2ENR;
237  (void) tmpreg;
238#endif /* DATA_IN_D2_SRAM */
239#else /* __rtems__ */
240  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
241  RCC->AHB2ENR;
242#endif /* __rtems__ */
243
244#ifndef __rtems__
245#if defined(DUAL_CORE) && defined(CORE_CM4)
246  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
247#ifdef VECT_TAB_SRAM
248  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
249#else
250  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
251#endif /* VECT_TAB_SRAM */
252
253#else
254
255  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
256#ifdef VECT_TAB_SRAM
257  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
258#else
259  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
260#endif
261
262#endif /*DUAL_CORE && CORE_CM4*/
263#else /* __rtems__ */
264  SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
265#endif /* __rtems__ */
266
267}
268
269/**
270   * @brief  Update SystemCoreClock variable according to Clock Register Values.
271  *         The SystemCoreClock variable contains the core clock , it can
272  *         be used by the user application to setup the SysTick timer or configure
273  *         other parameters.
274  *
275  * @note   Each time the core clock changes, this function must be called
276  *         to update SystemCoreClock variable value. Otherwise, any configuration
277  *         based on this variable will be incorrect.
278  *
279  * @note   - The system frequency computed by this function is not the real
280  *           frequency in the chip. It is calculated based on the predefined
281  *           constant and the selected clock source:
282  *
283  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
284  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
285  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
286  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
287  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
288  *
289  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
290  *             4 MHz) but the real value may vary depending on the variations
291  *             in voltage and temperature.
292  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
293  *             64 MHz) but the real value may vary depending on the variations
294  *             in voltage and temperature.
295  *
296  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
297  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
298  *              frequency of the crystal used. Otherwise, this function may
299  *              have wrong result.
300  *
301  *         - The result of this function could be not correct when using fractional
302  *           value for HSE crystal.
303  * @param  None
304  * @retval None
305  */
306void SystemCoreClockUpdate (void)
307{
308  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
309  uint32_t common_system_clock;
310  float_t fracn1, pllvco;
311
312
313  /* Get SYSCLK source -------------------------------------------------------*/
314
315  switch (RCC->CFGR & RCC_CFGR_SWS)
316  {
317  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
318    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
319    break;
320
321  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
322    common_system_clock = CSI_VALUE;
323    break;
324
325  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
326    common_system_clock = HSE_VALUE;
327    break;
328
329  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
330
331    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
332    SYSCLK = PLL_VCO / PLLR
333    */
334    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
335    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
336    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
337    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
338
339    if (pllm != 0U)
340    {
341      switch (pllsource)
342      {
343        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
344
345        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
346        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
347
348        break;
349
350        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
351          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
352        break;
353
354        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
355          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
356        break;
357
358      default:
359          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
360        break;
361      }
362      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
363      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
364    }
365    else
366    {
367      common_system_clock = 0U;
368    }
369    break;
370
371  default:
372    common_system_clock = CSI_VALUE;
373    break;
374  }
375
376  /* Compute SystemClock frequency --------------------------------------------------*/
377#if defined (RCC_D1CFGR_D1CPRE)
378  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
379
380  /* common_system_clock frequency : CM7 CPU frequency  */
381  common_system_clock >>= tmp;
382
383  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
384  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
385
386#else
387  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
388
389  /* common_system_clock frequency : CM7 CPU frequency  */
390  common_system_clock >>= tmp;
391
392  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
393  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
394
395#endif
396
397#if defined(DUAL_CORE) && defined(CORE_CM4)
398  SystemCoreClock = SystemD2Clock;
399#else
400  SystemCoreClock = common_system_clock;
401#endif /* DUAL_CORE && CORE_CM4 */
402}
403
404
405/**
406  * @}
407  */
408
409/**
410  * @}
411  */
412
413/**
414  * @}
415  */
416/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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