source: rtems/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/system_stm32h7xx.c @ 1a4e78b3

Last change on this file since 1a4e78b3 was 1a4e78b3, checked in by Karel Gardas <karel@…>, on 03/09/23 at 13:15:53

bsps/stm32h7: fix propagation of configured HSE freq. value into the code

Sponsored-By: Precidata
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1/**
2  ******************************************************************************
3  * @file    system_stm32h7xx.c
4  * @author  MCD Application Team
5  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
6  *
7  *   This file provides two functions and one global variable to be called from
8  *   user application:
9  *      - SystemInit(): This function is called at startup just after reset and
10  *                      before branch to main program. This call is made inside
11  *                      the "startup_stm32h7xx.s" file.
12  *
13  *      - SystemCoreClock variable: Contains the core clock, it can be used
14  *                                  by the user application to setup the SysTick
15  *                                  timer or configure other parameters.
16  *
17  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18  *                                 be called whenever the core clock is changed
19  *                                 during program execution.
20  *
21  *
22  ******************************************************************************
23  * @attention
24  *
25  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26  * All rights reserved.</center></h2>
27  *
28  * This software component is licensed by ST under BSD 3-Clause license,
29  * the "License"; You may not use this file except in compliance with the
30  * License. You may obtain a copy of the License at:
31  *                        opensource.org/licenses/BSD-3-Clause
32  *
33  ******************************************************************************
34  */
35
36/** @addtogroup CMSIS
37  * @{
38  */
39
40/** @addtogroup stm32h7xx_system
41  * @{
42  */
43
44/** @addtogroup STM32H7xx_System_Private_Includes
45  * @{
46  */
47
48#include "stm32h7xx.h"
49#include <math.h>
50#ifdef __rtems__
51#include <bsp/linker-symbols.h>
52#include <bspopts.h>
53
54#define HSE_VALUE STM32H7_HSE_FREQUENCY
55
56#endif /* __rtems__ */
57#if !defined  (HSE_VALUE)
58#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
59#endif /* HSE_VALUE */
60
61#if !defined  (CSI_VALUE)
62  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
63#endif /* CSI_VALUE */
64
65#if !defined  (HSI_VALUE)
66  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
67#endif /* HSI_VALUE */
68
69
70/**
71  * @}
72  */
73
74/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
75  * @{
76  */
77
78/**
79  * @}
80  */
81
82/** @addtogroup STM32H7xx_System_Private_Defines
83  * @{
84  */
85
86/************************* Miscellaneous Configuration ************************/
87/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
88/* #define DATA_IN_D2_SRAM */
89
90/*!< Uncomment the following line if you need to relocate your vector Table in
91     Internal SRAM. */
92/* #define VECT_TAB_SRAM */
93#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
94                                      This value must be a multiple of 0x200. */
95/******************************************************************************/
96
97/**
98  * @}
99  */
100
101/** @addtogroup STM32H7xx_System_Private_Macros
102  * @{
103  */
104
105/**
106  * @}
107  */
108
109/** @addtogroup STM32H7xx_System_Private_Variables
110  * @{
111  */
112  /* This variable is updated in three ways:
113      1) by calling CMSIS function SystemCoreClockUpdate()
114      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
115      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
116         Note: If you use this function to configure the system clock; then there
117               is no need to call the 2 first functions listed above, since SystemCoreClock
118               variable is updated automatically.
119  */
120#ifndef __rtems__
121  uint32_t SystemCoreClock = 64000000;
122  uint32_t SystemD2Clock = 64000000;
123#else /* __rtems__ */
124  RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
125  RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
126#endif /* __rtems__ */
127  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
128
129/**
130  * @}
131  */
132
133/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
134  * @{
135  */
136
137/**
138  * @}
139  */
140
141/** @addtogroup STM32H7xx_System_Private_Functions
142  * @{
143  */
144
145/**
146  * @brief  Setup the microcontroller system
147  *         Initialize the FPU setting and  vector table location
148  *         configuration.
149  * @param  None
150  * @retval None
151  */
152void SystemInit (void)
153{
154#if defined (DATA_IN_D2_SRAM)
155 __IO uint32_t tmpreg;
156#endif /* DATA_IN_D2_SRAM */
157
158  /* FPU settings ------------------------------------------------------------*/
159  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
160    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
161  #endif
162  /* Reset the RCC clock configuration to the default reset state ------------*/
163  /* Set HSION bit */
164  RCC->CR |= RCC_CR_HSION;
165
166  /* Reset CFGR register */
167  RCC->CFGR = 0x00000000;
168
169  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
170  RCC->CR &= 0xEAF6ED7FU;
171
172#if defined(D3_SRAM_BASE)
173  /* Reset D1CFGR register */
174  RCC->D1CFGR = 0x00000000;
175
176  /* Reset D2CFGR register */
177  RCC->D2CFGR = 0x00000000;
178
179  /* Reset D3CFGR register */
180  RCC->D3CFGR = 0x00000000;
181#else
182  /* Reset CDCFGR1 register */
183  RCC->CDCFGR1 = 0x00000000;
184
185  /* Reset CDCFGR2 register */
186  RCC->CDCFGR2 = 0x00000000;
187
188  /* Reset SRDCFGR register */
189  RCC->SRDCFGR = 0x00000000;
190#endif
191  /* Reset PLLCKSELR register */
192  RCC->PLLCKSELR = 0x00000000;
193
194  /* Reset PLLCFGR register */
195  RCC->PLLCFGR = 0x00000000;
196  /* Reset PLL1DIVR register */
197  RCC->PLL1DIVR = 0x00000000;
198  /* Reset PLL1FRACR register */
199  RCC->PLL1FRACR = 0x00000000;
200
201  /* Reset PLL2DIVR register */
202  RCC->PLL2DIVR = 0x00000000;
203
204  /* Reset PLL2FRACR register */
205
206  RCC->PLL2FRACR = 0x00000000;
207  /* Reset PLL3DIVR register */
208  RCC->PLL3DIVR = 0x00000000;
209
210  /* Reset PLL3FRACR register */
211  RCC->PLL3FRACR = 0x00000000;
212
213  /* Reset HSEBYP bit */
214  RCC->CR &= 0xFFFBFFFFU;
215
216  /* Disable all interrupts */
217  RCC->CIER = 0x00000000;
218
219#if (STM32H7_DEV_ID == 0x450UL)
220  /* dual core CM7 or single core line */
221  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
222  {
223    /* if stm32h7 revY*/
224    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
225    *((__IO uint32_t*)0x51008108) = 0x000000001U;
226  }
227#endif
228
229#ifndef __rtems__
230#if defined (DATA_IN_D2_SRAM)
231  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
232#if defined(RCC_AHB2ENR_D2SRAM3EN)
233  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
234#elif defined(RCC_AHB2ENR_D2SRAM2EN)
235  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
236#else
237  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
238#endif /* RCC_AHB2ENR_D2SRAM3EN */
239
240  tmpreg = RCC->AHB2ENR;
241  (void) tmpreg;
242#endif /* DATA_IN_D2_SRAM */
243#else /* __rtems__ */
244  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
245  RCC->AHB2ENR;
246#endif /* __rtems__ */
247
248#ifndef __rtems__
249#if defined(DUAL_CORE) && defined(CORE_CM4)
250  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
251#ifdef VECT_TAB_SRAM
252  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
253#else
254  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
255#endif /* VECT_TAB_SRAM */
256
257#else
258
259  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
260#ifdef VECT_TAB_SRAM
261  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
262#else
263  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
264#endif
265
266#endif /*DUAL_CORE && CORE_CM4*/
267#else /* __rtems__ */
268  SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
269#endif /* __rtems__ */
270
271}
272
273/**
274   * @brief  Update SystemCoreClock variable according to Clock Register Values.
275  *         The SystemCoreClock variable contains the core clock , it can
276  *         be used by the user application to setup the SysTick timer or configure
277  *         other parameters.
278  *
279  * @note   Each time the core clock changes, this function must be called
280  *         to update SystemCoreClock variable value. Otherwise, any configuration
281  *         based on this variable will be incorrect.
282  *
283  * @note   - The system frequency computed by this function is not the real
284  *           frequency in the chip. It is calculated based on the predefined
285  *           constant and the selected clock source:
286  *
287  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
288  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
289  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
290  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
291  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
292  *
293  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
294  *             4 MHz) but the real value may vary depending on the variations
295  *             in voltage and temperature.
296  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
297  *             64 MHz) but the real value may vary depending on the variations
298  *             in voltage and temperature.
299  *
300  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
301  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
302  *              frequency of the crystal used. Otherwise, this function may
303  *              have wrong result.
304  *
305  *         - The result of this function could be not correct when using fractional
306  *           value for HSE crystal.
307  * @param  None
308  * @retval None
309  */
310void SystemCoreClockUpdate (void)
311{
312  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
313  uint32_t common_system_clock;
314  float_t fracn1, pllvco;
315
316
317  /* Get SYSCLK source -------------------------------------------------------*/
318
319  switch (RCC->CFGR & RCC_CFGR_SWS)
320  {
321  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
322    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
323    break;
324
325  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
326    common_system_clock = CSI_VALUE;
327    break;
328
329  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
330    common_system_clock = HSE_VALUE;
331    break;
332
333  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
334
335    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
336    SYSCLK = PLL_VCO / PLLR
337    */
338    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
339    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
340    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
341    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
342
343    if (pllm != 0U)
344    {
345      switch (pllsource)
346      {
347        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
348
349        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
350        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
351
352        break;
353
354        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
355          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
356        break;
357
358        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
359          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
360        break;
361
362      default:
363          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
364        break;
365      }
366      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
367      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
368    }
369    else
370    {
371      common_system_clock = 0U;
372    }
373    break;
374
375  default:
376    common_system_clock = CSI_VALUE;
377    break;
378  }
379
380  /* Compute SystemClock frequency --------------------------------------------------*/
381#if defined (RCC_D1CFGR_D1CPRE)
382  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
383
384  /* common_system_clock frequency : CM7 CPU frequency  */
385  common_system_clock >>= tmp;
386
387  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
388  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
389
390#else
391  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
392
393  /* common_system_clock frequency : CM7 CPU frequency  */
394  common_system_clock >>= tmp;
395
396  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
397  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
398
399#endif
400
401#if defined(DUAL_CORE) && defined(CORE_CM4)
402  SystemCoreClock = SystemD2Clock;
403#else
404  SystemCoreClock = common_system_clock;
405#endif /* DUAL_CORE && CORE_CM4 */
406}
407
408
409/**
410  * @}
411  */
412
413/**
414  * @}
415  */
416
417/**
418  * @}
419  */
420/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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