1 | /* |
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2 | * Copyright (c) 2012 Sebastian Huber. All rights reserved. |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #include <bsp.h> |
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10 | #include <bsp/io.h> |
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11 | #include <bsp/irq.h> |
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12 | #include <bsp/bootcard.h> |
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13 | #include <bsp/irq-generic.h> |
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14 | #include <assert.h> |
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15 | #include <bsp/stm32f4.h> |
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16 | |
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17 | #ifdef STM32F4_FAMILY_F4XXXX |
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18 | |
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19 | #include <bsp/stm32f4xxxx_rcc.h> |
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20 | #include <bsp/stm32f4xxxx_flash.h> |
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21 | |
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22 | static rtems_status_code set_system_clk( |
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23 | uint32_t sys_clk, |
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24 | uint32_t hse_clk, |
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25 | uint32_t hse_flag |
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26 | ); |
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27 | |
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28 | static void init_main_osc( void ) |
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29 | { |
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30 | volatile stm32f4_rcc *rcc = STM32F4_RCC; |
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31 | rtems_status_code status; |
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32 | |
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33 | /* Revert to reset values */ |
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34 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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35 | |
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36 | while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ; |
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37 | |
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38 | rcc->cfgr &= 0x00000300; /* all prescalers to 0, clock source to HSI */ |
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39 | |
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40 | rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */ |
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41 | |
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42 | status = set_system_clk( STM32F4_SYSCLK / 1000000L, |
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43 | STM32F4_HSE_OSCILLATOR / 1000000L, |
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44 | 1 ); |
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45 | |
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46 | assert( rtems_is_status_successful( status ) ); |
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47 | } |
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48 | |
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49 | /** |
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50 | * @brief Sets up clocks configuration. |
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51 | * |
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52 | * Set up clocks configuration to achieve desired system clock |
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53 | * as close as possible with simple math. |
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54 | * |
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55 | * Limitations: |
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56 | * It is assumed that 1MHz resolution is enough. |
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57 | * Best fits for the clocks are achieved with multiplies of 42MHz. |
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58 | * Even though APB1, APB2 and AHB are calculated user is still required |
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59 | * to provide correct values for the bsp configuration for the: |
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60 | * STM32F4_PCLK1 |
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61 | * STM32F4_PCLK2 |
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62 | * STM32F4_HCLK |
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63 | * as those are used for the peripheral clocking calculations. |
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64 | * |
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65 | * @param sys_clk Desired system clock in MHz. |
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66 | * @param hse_clk External clock speed in MHz. |
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67 | * @param hse_flag Flag determining which clock source to use, 1 for HSE, |
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68 | * 0 for HSI. |
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69 | * |
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70 | * @retval RTEMS_SUCCESSFUL Configuration has been succesfully aplied for the |
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71 | * requested clock speed. |
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72 | * @retval RTEMS_TIMEOUT HSE clock didn't start or PLL didn't lock. |
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73 | * @retval RTEMS_INVALID_NUMBER Requested clock speed is out of range. |
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74 | */ |
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75 | static rtems_status_code set_system_clk( |
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76 | uint32_t sys_clk, |
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77 | uint32_t hse_clk, |
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78 | uint32_t hse_flag |
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79 | ) |
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80 | { |
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81 | volatile stm32f4_rcc *rcc = STM32F4_RCC; |
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82 | volatile stm32f4_flash *flash = STM32F4_FLASH; |
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83 | long timeout = 0; |
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84 | |
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85 | int src_clk = 0; |
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86 | |
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87 | uint32_t pll_m = 0; |
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88 | uint32_t pll_n = 0; |
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89 | uint32_t pll_p = 0; |
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90 | uint32_t pll_q = 0; |
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91 | |
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92 | uint32_t ahbpre = 0; |
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93 | uint32_t apbpre1 = 0; |
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94 | uint32_t apbpre2 = 0; |
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95 | |
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96 | if ( sys_clk == 16 && hse_clk != 16 ) { |
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97 | /* Revert to reset values */ |
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98 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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99 | |
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100 | while ( !( rcc->cr & RCC_CR_HSIRDY ) ) ; |
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101 | |
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102 | /* all prescalers to 0, clock source to HSI */ |
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103 | rcc->cfgr &= 0x00000300 | RCC_CFGR_SW_HSI; |
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104 | rcc->cr &= 0xF0F0FFFD; /* turn off all clocks and PLL except HSI */ |
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105 | flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */ |
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106 | |
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107 | return RTEMS_SUCCESSFUL; |
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108 | } |
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109 | |
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110 | if ( sys_clk == hse_clk ) { |
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111 | /* Revert to reset values */ |
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112 | rcc->cr |= RCC_CR_HSEON; /* turn on HSE */ |
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113 | timeout = 400; |
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114 | |
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115 | while ( !( rcc->cr & RCC_CR_HSERDY ) && --timeout ) ; |
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116 | |
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117 | assert( timeout != 0 ); |
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118 | |
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119 | if ( timeout == 0 ) { |
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120 | return RTEMS_TIMEOUT; |
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121 | } |
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122 | |
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123 | /* all prescalers to 0, clock source to HSE */ |
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124 | rcc->cfgr &= 0x00000300; |
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125 | rcc->cfgr |= RCC_CFGR_SW_HSE; |
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126 | /* turn off all clocks and PLL except HSE */ |
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127 | rcc->cr &= 0xF0F0FFFC | RCC_CR_HSEON; |
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128 | flash->acr = 0; /* slow clock so no cache, no prefetch, no latency */ |
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129 | |
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130 | return RTEMS_SUCCESSFUL; |
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131 | } |
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132 | |
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133 | /* |
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134 | * Lets use 1MHz input for PLL so we get higher VCO output |
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135 | * this way we get better value for the PLL_Q divader for the USB |
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136 | * |
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137 | * Though you might want to use 2MHz as per CPU specification: |
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138 | * |
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139 | * Caution:The software has to set these bits correctly to ensure |
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140 | * that the VCO input frequency ranges from 1 to 2 MHz. |
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141 | * It is recommended to select a frequency of 2 MHz to limit PLL jitter. |
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142 | */ |
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143 | |
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144 | if ( sys_clk > 180 ) { |
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145 | return RTEMS_INVALID_NUMBER; |
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146 | } else if ( sys_clk >= 96 ) { |
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147 | pll_n = sys_clk << 1; |
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148 | pll_p = RCC_PLLCFGR_PLLP_BY_2; |
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149 | } else if ( sys_clk >= 48 ) { |
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150 | pll_n = sys_clk << 2; |
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151 | pll_p = RCC_PLLCFGR_PLLP_BY_4; |
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152 | } else if ( sys_clk >= 24 ) { |
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153 | pll_n = sys_clk << 3; |
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154 | pll_p = RCC_PLLCFGR_PLLP_BY_8; |
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155 | } else { |
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156 | return RTEMS_INVALID_NUMBER; |
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157 | } |
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158 | |
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159 | if ( hse_clk == 0 || hse_flag == 0 ) { |
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160 | src_clk = 16; |
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161 | hse_flag = 0; |
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162 | } else { |
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163 | src_clk = hse_clk; |
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164 | } |
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165 | |
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166 | pll_m = src_clk; /* divide by the oscilator speed in MHz */ |
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167 | |
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168 | /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG, |
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169 | * best if results in the 48MHz for the USB |
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170 | */ |
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171 | pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; |
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172 | |
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173 | if ( pll_q < 2 ) { |
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174 | pll_q = 2; |
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175 | } |
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176 | |
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177 | /* APB1 prescaler, APB1 clock must be < 42MHz */ |
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178 | apbpre1 = ( sys_clk * 100 ) / 42; |
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179 | |
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180 | if ( apbpre1 <= 100 ) { |
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181 | apbpre1 = RCC_CFGR_PPRE1_BY_1; |
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182 | } else if ( apbpre1 <= 200 ) { |
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183 | apbpre1 = RCC_CFGR_PPRE1_BY_2; |
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184 | } else if ( apbpre1 <= 400 ) { |
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185 | apbpre1 = RCC_CFGR_PPRE1_BY_4; |
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186 | } else if ( apbpre1 <= 800 ) { |
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187 | apbpre1 = RCC_CFGR_PPRE1_BY_8; |
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188 | } else if ( apbpre1 ) { |
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189 | apbpre1 = RCC_CFGR_PPRE1_BY_16; |
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190 | } |
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191 | |
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192 | /* APB2 prescaler, APB2 clock must be < 84MHz */ |
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193 | apbpre2 = ( sys_clk * 100 ) / 84; |
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194 | |
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195 | if ( apbpre2 <= 100 ) { |
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196 | apbpre2 = RCC_CFGR_PPRE2_BY_1; |
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197 | } else if ( apbpre2 <= 200 ) { |
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198 | apbpre2 = RCC_CFGR_PPRE2_BY_2; |
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199 | } else if ( apbpre2 <= 400 ) { |
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200 | apbpre2 = RCC_CFGR_PPRE2_BY_4; |
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201 | } else if ( apbpre2 <= 800 ) { |
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202 | apbpre2 = RCC_CFGR_PPRE2_BY_8; |
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203 | } else { |
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204 | apbpre2 = RCC_CFGR_PPRE2_BY_16; |
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205 | } |
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206 | |
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207 | rcc->cr |= RCC_CR_HSION; /* turn on HSI */ |
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208 | |
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209 | while ( ( !( rcc->cr & RCC_CR_HSIRDY ) ) ) ; |
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210 | |
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211 | /* all prescalers to 0, clock source to HSI */ |
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212 | rcc->cfgr &= 0x00000300; |
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213 | rcc->cfgr |= RCC_CFGR_SW_HSI; |
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214 | |
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215 | while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_HSI ) ) ; |
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216 | |
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217 | /* turn off PLL */ |
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218 | rcc->cr &= ~( RCC_CR_PLLON | RCC_CR_PLLRDY ); |
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219 | |
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220 | /* turn on HSE */ |
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221 | if ( hse_flag ) { |
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222 | rcc->cr |= RCC_CR_HSEON; |
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223 | timeout = 400; |
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224 | |
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225 | while ( ( !( rcc->cr & RCC_CR_HSERDY ) ) && timeout-- ) ; |
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226 | |
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227 | assert( timeout != 0 ); |
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228 | |
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229 | if ( timeout == 0 ) { |
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230 | return RTEMS_TIMEOUT; |
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231 | } |
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232 | } |
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233 | |
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234 | rcc->pllcfgr &= 0xF0BC8000; /* clear PLL prescalers */ |
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235 | |
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236 | /* set pll parameters */ |
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237 | rcc->pllcfgr |= RCC_PLLCFGR_PLLM( pll_m ) | /* input divider */ |
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238 | RCC_PLLCFGR_PLLN( pll_n ) | /* multiplier */ |
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239 | pll_p | /* output divider from table */ |
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240 | /* HSE v HSI */ |
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241 | ( hse_flag ? RCC_PLLCFGR_PLLSRC_HSE : RCC_PLLCFGR_PLLSRC_HSI ) |
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242 | | |
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243 | RCC_PLLCFGR_PLLQ( pll_q ); /* PLLQ divider */ |
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244 | |
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245 | /* set prescalers for the internal busses */ |
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246 | rcc->cfgr |= apbpre1 | |
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247 | apbpre2 | |
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248 | ahbpre; |
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249 | |
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250 | /* |
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251 | * Set flash parameters, hard coded for now for fast system clocks. |
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252 | * TODO implement some math to use flash on as low latancy as possible |
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253 | */ |
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254 | flash->acr = STM32F4_FLASH_ACR_LATENCY( 5 ) | /* latency */ |
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255 | STM32F4_FLASH_ACR_ICEN | /* instruction cache */ |
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256 | STM32F4_FLASH_ACR_DCEN | /* data cache */ |
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257 | STM32F4_FLASH_ACR_PRFTEN; |
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258 | |
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259 | /* turn on PLL */ |
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260 | rcc->cr |= RCC_CR_PLLON; |
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261 | timeout = 40000; |
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262 | |
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263 | while ( ( !( rcc->cr & RCC_CR_PLLRDY ) ) && --timeout ) ; |
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264 | |
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265 | assert( timeout != 0 ); |
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266 | |
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267 | if ( timeout == 0 ) { |
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268 | return RTEMS_TIMEOUT; |
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269 | } |
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270 | |
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271 | /* clock source to PLL */ |
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272 | rcc->cfgr = ( rcc->cfgr & ~RCC_CFGR_SW_MSK ) | RCC_CFGR_SW_PLL; |
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273 | |
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274 | while ( ( ( rcc->cfgr & RCC_CFGR_SWS_MSK ) != RCC_CFGR_SWS_PLL ) ) ; |
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275 | |
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276 | return RTEMS_SUCCESSFUL; |
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277 | } |
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278 | |
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279 | #endif /* STM32F4_FAMILY_F4XXXX */ |
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280 | |
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281 | #ifdef STM32F4_FAMILY_F10XXX |
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282 | |
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283 | static void init_main_osc( void ) |
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284 | { |
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285 | |
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286 | } |
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287 | |
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288 | #endif /* STM32F4_FAMILY_F10XXX */ |
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289 | |
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290 | void bsp_start( void ) |
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291 | { |
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292 | init_main_osc(); |
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293 | |
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294 | stm32f4_gpio_set_config_array( &stm32f4_start_config_gpio[ 0 ] ); |
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295 | |
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296 | bsp_interrupt_initialize(); |
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297 | } |
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