1 | /* |
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2 | * Copyright (c) 2013 Chris Nott. All rights reserved. |
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3 | * |
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4 | * Virtual Logic |
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5 | * 21-25 King St. |
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6 | * Rockdale NSW 2216 |
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7 | * Australia |
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8 | * <rtems@vl.com.au> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H |
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16 | #define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H |
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17 | |
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18 | #include <bsp/utility.h> |
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19 | |
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20 | struct stm32f4_tim_s { |
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21 | uint16_t cr1; // Control register 1 |
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22 | #define STM32F4_TIMER_CR1_CKD_DIV 0x0300 |
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23 | #define STM32F4_TIMER_CR1_CKD_DIV1 0x0000 |
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24 | #define STM32F4_TIMER_CR1_CKD_DIV2 0x0100 |
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25 | #define STM32F4_TIMER_CR1_CKD_DIV3 0x0200 |
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26 | #define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7) |
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27 | #define STM32F4_TIMER_CR1_CMS 0x0060 |
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28 | #define STM32F4_TIMER_CR1_CMS_EDGE 0x0000 |
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29 | #define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020 |
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30 | #define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040 |
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31 | #define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060 |
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32 | #define STM32F4_TIMER_CR1_DIR BSP_BIT16(4) |
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33 | #define STM32F4_TIMER_CR1_DIR_UP 0x0000 |
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34 | #define STM32F4_TIMER_CR1_DIR_DOWN 0x0010 |
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35 | #define STM32F4_TIMER_CR1_DIR_OPM 0x0008 |
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36 | #define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000 |
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37 | #define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008 |
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38 | #define STM32F4_TIMER_CR1_DIR_URS 0x0004 |
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39 | #define STM32F4_TIMER_CR1_DIR_UDIS 0x0002 |
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40 | #define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000 |
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41 | #define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002 |
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42 | #define STM32F4_TIMER_CR1_CEN 0x0001 |
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43 | uint16_t reserved_02; |
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44 | uint16_t cr2; // Control register 2 |
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45 | uint16_t reserved_06; |
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46 | uint16_t smcr; // Slave mode control register |
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47 | uint16_t reserved_0a; |
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48 | uint16_t dier; // DMA / interrupt enable register |
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49 | #define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable |
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50 | #define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable |
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51 | #define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable |
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52 | #define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable |
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53 | #define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable |
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54 | #define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable |
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55 | #define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable |
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56 | #define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable |
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57 | #define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable |
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58 | #define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable |
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59 | #define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable |
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60 | #define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable |
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61 | |
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62 | uint16_t reserved_0e; |
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63 | uint16_t sr; // Status register |
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64 | #define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag |
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65 | #define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag |
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66 | #define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag |
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67 | #define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag |
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68 | #define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag |
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69 | #define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag |
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70 | #define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag |
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71 | #define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag |
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72 | #define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag |
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73 | #define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag |
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74 | uint16_t reserved_12; |
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75 | uint16_t egr; // Event generation register |
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76 | #define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event |
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77 | #define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event |
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78 | #define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation) |
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79 | #define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation) |
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80 | #define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation) |
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81 | #define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event |
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82 | uint16_t reserved_16; |
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83 | uint16_t ccmr1; // Capture / compare mode register 1 |
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84 | #define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable |
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85 | #define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14) |
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86 | #define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14) |
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87 | #define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) |
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88 | #define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0) |
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89 | #define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1) |
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90 | #define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2) |
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91 | #define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3) |
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92 | #define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4) |
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93 | #define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5) |
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94 | #define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6) |
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95 | #define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7) |
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96 | #define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable |
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97 | #define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable |
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98 | #define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9) |
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99 | #define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9) |
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100 | #define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) |
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101 | #define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0) |
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102 | #define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1) |
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103 | #define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2) |
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104 | #define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3) |
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105 | #define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable |
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106 | #define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6) |
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107 | #define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6) |
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108 | #define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) |
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109 | #define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0) |
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110 | #define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1) |
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111 | #define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2) |
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112 | #define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3) |
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113 | #define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4) |
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114 | #define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5) |
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115 | #define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6) |
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116 | #define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7) |
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117 | #define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable |
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118 | #define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable |
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119 | #define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1) |
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120 | #define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1) |
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121 | #define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) |
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122 | #define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0) |
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123 | #define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1) |
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124 | #define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2) |
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125 | #define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3) |
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126 | uint16_t reserved_1a; |
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127 | uint16_t ccmr2; // Capture / compare mode register 2 |
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128 | #define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable |
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129 | #define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14) |
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130 | #define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14) |
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131 | #define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) |
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132 | #define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0) |
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133 | #define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1) |
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134 | #define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2) |
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135 | #define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3) |
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136 | #define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4) |
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137 | #define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5) |
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138 | #define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6) |
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139 | #define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7) |
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140 | #define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable |
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141 | #define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable |
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142 | #define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9) |
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143 | #define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9) |
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144 | #define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) |
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145 | #define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0) |
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146 | #define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1) |
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147 | #define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2) |
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148 | #define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3) |
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149 | #define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable |
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150 | #define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6) |
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151 | #define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6) |
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152 | #define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) |
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153 | #define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0) |
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154 | #define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1) |
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155 | #define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2) |
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156 | #define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3) |
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157 | #define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4) |
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158 | #define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5) |
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159 | #define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6) |
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160 | #define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7) |
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161 | #define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable |
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162 | #define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable |
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163 | #define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1) |
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164 | #define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1) |
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165 | #define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) |
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166 | #define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0) |
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167 | #define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1) |
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168 | #define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2) |
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169 | #define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3) |
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170 | uint16_t reserved_1e; |
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171 | uint16_t ccer; // Capture / compare enable register |
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172 | #define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity |
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173 | #define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity |
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174 | #define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable |
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175 | #define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity |
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176 | #define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity |
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177 | #define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable |
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178 | #define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity |
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179 | #define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity |
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180 | #define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable |
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181 | #define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity |
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182 | #define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity |
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183 | #define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable |
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184 | uint16_t reserved_22; |
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185 | uint32_t cnt; // Counter register |
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186 | #define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31) |
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187 | #define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31) |
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188 | #define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) |
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189 | uint16_t psc; // Prescalar |
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190 | uint16_t reserved_2a; |
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191 | uint32_t arr; // Auto-reload register |
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192 | uint16_t rcr; // Repetition counter register |
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193 | uint16_t rserved_32; |
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194 | uint32_t ccr[4];// Capture / compare registers |
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195 | uint16_t bdtr; // Break and dead-time register |
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196 | uint16_t reserved_46; |
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197 | uint16_t dcr; // DMA control register |
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198 | uint16_t reserved_4a; |
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199 | uint16_t dmar; // DMA address for full transfer |
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200 | uint16_t reserved_4e; |
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201 | uint16_t or; // Option register |
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202 | uint16_t reserved_52; |
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203 | } __attribute__ ((packed)); |
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204 | typedef struct stm32f4_tim_s stm32f4_tim; |
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205 | |
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206 | #endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */ |
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